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author | Rob Herring (Arm) <robh@kernel.org> | 2024-10-02 13:43:24 -0500 |
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committer | Will Deacon <will@kernel.org> | 2024-10-28 17:27:15 +0000 |
commit | 0bbff9ed81654d5f06bfca484681756ee407f924 (patch) | |
tree | 10ab083995cee3f3802c0ffa2b076dfcfa50d08a /arch/arm64/tools | |
parent | 759b5fc6cc3e3c5841f6a3e4638b39534b0fc716 (diff) | |
download | lwn-0bbff9ed81654d5f06bfca484681756ee407f924.tar.gz lwn-0bbff9ed81654d5f06bfca484681756ee407f924.zip |
perf/arm_pmuv3: Add PMUv3.9 per counter EL0 access control
Armv8.9/9.4 PMUv3.9 adds per counter EL0 access controls. Per counter
access is enabled with the UEN bit in PMUSERENR_EL1 register. Individual
counters are enabled/disabled in the PMUACR_EL1 register. When UEN is
set, the CR/ER bits control EL0 write access and must be set to disable
write access.
With the access controls, the clearing of unused counters can be
skipped.
KVM also configures PMUSERENR_EL1 in order to trap to EL2. UEN does not
need to be set for it since only PMUv3.5 is exposed to guests.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241002184326.1105499-1-robh@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch/arm64/tools')
-rw-r--r-- | arch/arm64/tools/sysreg | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 8d637ac4b7c6..74fb5af91d4f 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -1238,6 +1238,7 @@ UnsignedEnum 11:8 PMUVer 0b0110 V3P5 0b0111 V3P7 0b1000 V3P8 + 0b1001 V3P9 0b1111 IMP_DEF EndEnum UnsignedEnum 7:4 TraceVer @@ -2178,6 +2179,13 @@ Field 4 P Field 3:0 ALIGN EndSysreg +Sysreg PMUACR_EL1 3 0 9 14 4 +Res0 63:33 +Field 32 F0 +Field 31 C +Field 30:0 P +EndSysreg + Sysreg PMSELR_EL0 3 3 9 12 5 Res0 63:5 Field 4:0 SEL |