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| author | Qiang Yu <quic_qianyu@quicinc.com> | 2024-11-13 00:05:08 -0800 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2024-12-16 14:32:00 -0600 |
| commit | fb8e7b33c2174e00dfa411361eeed21eeaf3634b (patch) | |
| tree | 45ad64652c22a412e356f04855140372c5666c5f /arch/arm64/boot | |
| parent | 1fb5cf0d165afc3be76ec754d1b1013515c3896a (diff) | |
| download | lwn-fb8e7b33c2174e00dfa411361eeed21eeaf3634b.tar.gz lwn-fb8e7b33c2174e00dfa411361eeed21eeaf3634b.zip | |
arm64: dts: qcom: x1e80100: Fix up BAR space size for PCIe6a
As per memory map table, the region for PCIe6a is 64MByte. Hence, set the
size of 32 bit non-prefetchable memory region beginning on address
0x70300000 as 0x3d00000 so that BAR space assigned to BAR registers can be
allocated from 0x70300000 to 0x74000000.
Fixes: 7af141850012 ("arm64: dts: qcom: x1e80100: Fix up BAR spaces")
Cc: stable@vger.kernel.org
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241113080508.3458849-1-quic_qianyu@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 88805629ed2b..f1a1e63f8ebc 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2924,7 +2924,7 @@ #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, - <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>; + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; bus-range = <0x00 0xff>; dma-coherent; |