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authorKonrad Dybcio <konradybcio@gmail.com>2020-06-25 20:21:13 +0200
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-07-27 23:44:10 -0700
commit0835375212681cdf26d120a4fb792ed524f24447 (patch)
treeeaaffcc4074d5f16834070bb771118039166adb1 /arch/arm64/boot
parent7f8bcc0c4cfec4ea0340a4fc1e39f55126ebbece (diff)
downloadlwn-0835375212681cdf26d120a4fb792ed524f24447.tar.gz
lwn-0835375212681cdf26d120a4fb792ed524f24447.zip
arm64: dts: qcom: msm8992: Add PMU node
Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8992.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
index e8b801813f14..c4c9a108ae1e 100644
--- a/arch/arm64/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi
@@ -130,6 +130,11 @@
reg = <0 0 0 0>;
};
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;