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| author | Peng Fan <peng.fan@nxp.com> | 2022-11-17 17:54:01 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2022-11-19 11:10:11 +0800 |
| commit | a8ea275d16230e5272080d101c3ab88d400f49a6 (patch) | |
| tree | 072e9ea992290ce5d445ba6c8b221b9a002cfd9f /arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | |
| parent | c0c4c4562b7c8115e44d60547b4f7c039ceca92b (diff) | |
| download | lwn-a8ea275d16230e5272080d101c3ab88d400f49a6.tar.gz lwn-a8ea275d16230e5272080d101c3ab88d400f49a6.zip | |
arm64: dts: imx8mn-evk: enable uart1
Enable uart1 for BT usage
Configure the clock to source from IMX8MN_SYS_PLL1_80M, because the uart
could only support max 1.5M buadrate if using OSC_24M as clock source.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 2439b91e51d8..8fef980c4ab2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -247,6 +247,15 @@ status = "okay"; }; +&uart1 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MN_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &uart2 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -444,6 +453,15 @@ >; }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |