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authorMichael Walle <michael@walle.cc>2022-02-28 14:25:23 +0100
committerShawn Guo <shawnguo@kernel.org>2022-04-08 19:43:37 +0800
commit579df4288896f22c5e8c38aee771edc5f25bf461 (patch)
treeffa26322fc49139619258f0e02677c52f9733901 /arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
parent9694ed9bcf3b761c05d7787739eb4e77bd86c367 (diff)
downloadlwn-579df4288896f22c5e8c38aee771edc5f25bf461.tar.gz
lwn-579df4288896f22c5e8c38aee771edc5f25bf461.zip
arm64: dts: imx8mn-evk: add QSPI flash
There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. Add a device tree node for it. Tested on a 8MNANOD3L-EVK. Signed-off-by: Michael Walle <michael@walle.cc> Tested-by: Heiko Thiery <heiko.thiery@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index c3f15192b76c..dc75d6d13bb3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -110,6 +110,22 @@
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi>;
+ status = "okay";
+
+ flash0: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <166000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -267,6 +283,17 @@
>;
};
+ pinctrl_flexspi: flexspigrp {
+ fsl,pins = <
+ MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
+ MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19