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| author | Adam Ford <aford173@gmail.com> | 2020-10-07 09:24:08 -0500 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-10-30 16:01:20 +0800 |
| commit | 582b6d8b258d5bdc2dfde133145dc90fb9fea5e0 (patch) | |
| tree | ec6e73370b5a7377a4078a433e02bf46c5607bdb /arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | |
| parent | 56c6b4ddfd503ff4de31462c92a187ee440b796e (diff) | |
| download | lwn-582b6d8b258d5bdc2dfde133145dc90fb9fea5e0.tar.gz lwn-582b6d8b258d5bdc2dfde133145dc90fb9fea5e0.zip | |
arm64: dts: imx8mm-beacon-som: Add QSPI NOR flash support
imx8mm-beacon-som has a Quad-SPI NOR flash connected to the FlexSPI bus.
This patch enables the FlexSPI bus and configures it to work with the
flash part.
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 0b8c4e4ad45b..09ad2d71b8b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -75,6 +75,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -302,6 +318,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 |