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| author | Shawn Guo <shawn.guo@linaro.org> | 2015-04-26 13:33:39 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2015-06-03 14:44:32 +0800 |
| commit | 3bec5f8184125ad4441905aee1856ef0a57b66b1 (patch) | |
| tree | 01fa929eb4a7fdcc4973ae65f41487e421c95c7d /arch/arm/mach-imx/clk-imx1.c | |
| parent | 961dfd37fa165c8d5019648edcec966f28300959 (diff) | |
| download | lwn-3bec5f8184125ad4441905aee1856ef0a57b66b1.tar.gz lwn-3bec5f8184125ad4441905aee1856ef0a57b66b1.zip | |
ARM: imx: add clk-pllv1 type support
Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1
type support to handle the difference/quirk in particular SoC designs.
Doing so will help get clk-pllv1 driver ready for being moved out of
arch/arm/mach-imx folder.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/mach-imx/clk-imx1.c')
| -rw-r--r-- | arch/arm/mach-imx/clk-imx1.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c index 5301d2ebb234..9e68351bb72c 100644 --- a/arch/arm/mach-imx/clk-imx1.c +++ b/arch/arm/mach-imx/clk-imx1.c @@ -50,9 +50,9 @@ static void __init _mx1_clocks_init(unsigned long fref) clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)); - clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); + clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); - clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); + clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); |