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| author | Tigran Tadevosyan <tigran.tadevosyan@arm.com> | 2019-04-05 14:16:13 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2019-04-23 17:28:37 +0100 |
| commit | c3143967807adb1357c36b68a7563fc0c4e1f615 (patch) | |
| tree | 366d4c17a8d55bf9c4830fd67630c4f7b9dc7016 /arch/arm/boot | |
| parent | 503621628b32782a07b2318e4112bd4372aa3401 (diff) | |
| download | lwn-c3143967807adb1357c36b68a7563fc0c4e1f615.tar.gz lwn-c3143967807adb1357c36b68a7563fc0c4e1f615.zip | |
ARM: 8856/1: NOMMU: Fix CCR register faulty initialization when MPU is disabled
When CONFIG_ARM_MPU is not defined, the base address of v7M SCB register
is not initialized with correct value. This prevents enabling I/D caches
when the L1 cache poilcy is applied in kernel.
Fixes: 3c24121039c9da14692eb48f6e39565b28c0f3cf ("ARM: 8756/1: NOMMU: Postpone MPU activation till __after_proc_init")
Signed-off-by: Tigran Tadevosyan <tigran.tadevosyan@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/boot')
0 files changed, 0 insertions, 0 deletions