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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2017-07-14 11:42:46 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-07-17 15:27:26 +0100 |
| commit | f12a616e0cdee71440b72f7602825db424d37879 (patch) | |
| tree | 9d32ddb285cd70f4fa991cae35412d6cc0357cf9 /Makefile | |
| parent | 5771a8c08880cdca3bfb4a3fc6d309d6bba20877 (diff) | |
| download | lwn-f12a616e0cdee71440b72f7602825db424d37879.tar.gz lwn-f12a616e0cdee71440b72f7602825db424d37879.zip | |
spi: loopback-test: provide loop_req option.
Provide a module parameter to request internal loop by the SPI master
controller.
This should make loop testing easier without extra HW modification.
For test automation a logic analyzer is recommended for host
controller-independent verification.
An example test rig configuration and procedure:
i.MX6S RIoRBoard Logic Analyzer
-----------------------------------------
(J13 4) GND ------------- GND
(J13 6) CSPI3-CLK ------> PIN 3
(J13 8) CSPI3-MOSI <----- PIN 2
^ - internal loop configured by SPI_LOOP
| or can be user external jamper.
(J13 10) CSPI3-MISO -----> PIN 1
grab some data and decode it:
sigrok-cli -d fx2lafw --time 160000 --config samplerate=10m \
--channels 0-2 -o dump.sr
sigrok-cli -i dump.sr -P spi:mosi=1:clk=2 > result_for_regression_tests
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions