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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-06-10 17:29:20 +0200 |
|---|---|---|
| committer | Rob Herring (Arm) <robh@kernel.org> | 2026-06-12 09:11:41 -0500 |
| commit | f638ffe4dbafcd51df1f98fd659e5e672cc7e539 (patch) | |
| tree | 8835ca9accabb86fdbe756964aaae57cd47e50fc /Documentation | |
| parent | 8e45719acdd6bf0bb6bf083957b53e40340dcd41 (diff) | |
| download | lwn-f638ffe4dbafcd51df1f98fd659e5e672cc7e539.tar.gz lwn-f638ffe4dbafcd51df1f98fd659e5e672cc7e539.zip | |
dt-bindings: cache: l2c2x0: Add missing power-domains
On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
Controller is located in a controllable power area.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/0a57ab356e5f426e28ead373b809f88a63e55380.1781105151.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml index 10c1a900202f..ee604117ffb3 100644 --- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -66,6 +66,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + arm,data-latency: description: Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers |