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| author | Ammar Mustafa <ammarmustafa34@gmail.com> | 2026-02-27 14:08:33 -0500 |
|---|---|---|
| committer | Jonathan Cameron <Jonathan.Cameron@huawei.com> | 2026-03-27 07:31:19 +0000 |
| commit | d2a4ec19d2a2e54c23b5180e939994d3da4a6b91 (patch) | |
| tree | fafd605ff6cbc4d436abc97d996c68f31d9253ec /Documentation/iio | |
| parent | d185324efadc1e75acc6be2e4351ecfe8957b3a7 (diff) | |
| download | lwn-d2a4ec19d2a2e54c23b5180e939994d3da4a6b91.tar.gz lwn-d2a4ec19d2a2e54c23b5180e939994d3da4a6b91.zip | |
Docs: iio: ad7191 Correct clock configuration
Correct the ad7191 documentation to match the datasheet:
- Fix inverted CLKSEL pin logic: device uses external clock when pin is
inactive, and internal CMOS/crystal when high.
- Correct CMOS-compatible clock pin from MCLK2 to MCLK1.
Signed-off-by: Ammar Mustafa <ammarmustafa34@gmail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'Documentation/iio')
| -rw-r--r-- | Documentation/iio/ad7191.rst | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/iio/ad7191.rst b/Documentation/iio/ad7191.rst index 977d4fea14b0..fd6a23ad44fd 100644 --- a/Documentation/iio/ad7191.rst +++ b/Documentation/iio/ad7191.rst @@ -63,11 +63,11 @@ Clock Configuration The AD7191 supports both internal and external clock sources: -- When CLKSEL pin is tied LOW: Uses internal 4.92MHz clock (no clock property +- When CLKSEL pin is ACTIVE: Uses internal 4.92MHz clock (no clock property needed) -- When CLKSEL pin is tied HIGH: Requires external clock source +- When CLKSEL pin is INACTIVE: Requires external clock source - Can be a crystal between MCLK1 and MCLK2 pins - - Or a CMOS-compatible clock driving MCLK2 pin + - Or a CMOS-compatible clock driving MCLK1 pin and MCLK2 left unconnected - Must specify the "clocks" property in device tree when using external clock SPI Interface Requirements |