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| author | Zhi Li <lizhi2@eswincomputing.com> | 2026-06-02 09:45:28 +0800 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2026-06-04 08:30:37 -0700 |
| commit | 1232b3104b4b2c0267f31608fe0f8a8758428f28 (patch) | |
| tree | 3d70f4a4abc88100ad5d886e75831ddb62d15b6b /Documentation/devicetree | |
| parent | 0861615c28de668669d748ef4eb913ea9262d13b (diff) | |
| download | lwn-1232b3104b4b2c0267f31608fe0f8a8758428f28.tar.gz lwn-1232b3104b4b2c0267f31608fe0f8a8758428f28.zip | |
dt-bindings: ethernet: eswin: fix hsp-sp-csr backward compatibility
Commit c36069c6f46c ("dt-bindings: ethernet: eswin: add optional TXD and
RXD delay register offsets") added two optional cells to eswin,hsp-sp-csr
but omitted minItems: 4.
As a result, dt-schema implicitly required all 6 cells, which broke
backward compatibility with existing 4-cell device trees.
Add minItems: 4 to preserve backward compatibility.
Fixes: c36069c6f46c ("dt-bindings: ethernet: eswin: add optional TXD and RXD delay register offsets")
Reported-by: Sashiko AI <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/all/20260519022334.35742C2BCB7@smtp.kernel.org/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Zhi Li <lizhi2@eswincomputing.com>
Link: https://patch.msgid.link/20260602014528.2076-1-lizhi2@eswincomputing.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml index b66ae6300faf..65882ff79d8d 100644 --- a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -84,7 +84,8 @@ properties: This reference is provided for background information only. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - items: + - minItems: 4 + items: - description: Phandle to HSP(High-Speed Peripheral) device - description: Offset of phy control register for internal or external clock selection |