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| author | Matt Roper <matthew.d.roper@intel.com> | 2023-12-14 10:47:01 -0800 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-21 11:46:16 -0500 |
| commit | bc17ec0b201ec7b8576576aa0785787671b4afe7 (patch) | |
| tree | 866078e32a5625840966eccb8fca16c039419f2e | |
| parent | cbdc52c11c9b1df40ade23f622abc3466e4ee96c (diff) | |
| download | lwn-bc17ec0b201ec7b8576576aa0785787671b4afe7.tar.gz lwn-bc17ec0b201ec7b8576576aa0785787671b4afe7.zip | |
drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1
We don't use this suffix on any other registers, and it isn't part of
the register's official name either, so drop it for consistency.
While at it, move the register definition slightly so that it isn't
separating RING_CMD_CCTL's definition from its fields.
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231214184659.2249559-11-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_engine_regs.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa.c | 2 |
2 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h index 1a857c4edcf5..67da19f9836f 100644 --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h @@ -46,11 +46,6 @@ #define RING_ESR(base) XE_REG((base) + 0xb8) #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED) - -#define CSFE_CHICKEN1_REG(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) -#define GHWSP_CSB_REPORT_DIS REG_BIT(15) -#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) - /* * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. * The lsb of each can be considered a separate enabling bit for encryption. @@ -61,6 +56,10 @@ #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8) #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1) +#define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) +#define GHWSP_CSB_REPORT_DIS REG_BIT(15) +#define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) + #define RING_BBADDR(base) XE_REG((base) + 0x140) #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c index 23f1285135b8..12829748bb6c 100644 --- a/drivers/gpu/drm/xe/xe_wa.c +++ b/drivers/gpu/drm/xe/xe_wa.c @@ -605,7 +605,7 @@ static const struct xe_rtp_entry_sr engine_was[] = { */ { XE_RTP_NAME("18032095049, 16021639441"), XE_RTP_RULES(GRAPHICS_VERSION(2004)), - XE_RTP_ACTIONS(SET(CSFE_CHICKEN1_REG(0), + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), GHWSP_CSB_REPORT_DIS | PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, XE_RTP_ACTION_FLAG(ENGINE_BASE))) |