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authorJason Gunthorpe <jgg@nvidia.com>2026-03-26 16:30:32 -0300
committerJoerg Roedel <joerg.roedel@amd.com>2026-04-01 09:50:20 +0200
commit1c18a1212c772b6a19e8583f2fca73f3a47b60fd (patch)
tree2790e5f21559afa929cdba506568fb749f38a596
parenta11661a58c06f7fdfef03a368ef20d05a4ea4ed0 (diff)
downloadlwn-1c18a1212c772b6a19e8583f2fca73f3a47b60fd.tar.gz
lwn-1c18a1212c772b6a19e8583f2fca73f3a47b60fd.zip
iommu/dma: Always allow DMA-FQ when iommupt provides the iommu_domain
iommupt always supports the semantics required for DMA-FQ, when drivers are converted to use it they automatically get support. Detect iommpt directly instead of using IOMMU_CAP_DEFERRED_FLUSH and remove IOMMU_CAP_DEFERRED_FLUSH from converted drivers. This will also enable DMA-FQ on RISC-V. Signed-off-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
-rw-r--r--drivers/iommu/amd/iommu.c2
-rw-r--r--drivers/iommu/dma-iommu.c13
-rw-r--r--drivers/iommu/intel/iommu.c2
3 files changed, 12 insertions, 5 deletions
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index f1814fee5182..2e553e2051aa 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2978,8 +2978,6 @@ static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap)
return amdr_ivrs_remap_support;
case IOMMU_CAP_ENFORCE_CACHE_COHERENCY:
return true;
- case IOMMU_CAP_DEFERRED_FLUSH:
- return true;
case IOMMU_CAP_DIRTY_TRACKING: {
struct amd_iommu *iommu = get_amd_iommu_from_dev(dev);
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 5dac64be61bb..fbed93f8bf0a 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -14,6 +14,7 @@
#include <linux/device.h>
#include <linux/dma-direct.h>
#include <linux/dma-map-ops.h>
+#include <linux/generic_pt/iommu.h>
#include <linux/gfp.h>
#include <linux/huge_mm.h>
#include <linux/iommu.h>
@@ -648,6 +649,15 @@ static void iommu_dma_init_options(struct iommu_dma_options *options,
}
}
+static bool iommu_domain_supports_fq(struct device *dev,
+ struct iommu_domain *domain)
+{
+ /* iommupt always supports DMA-FQ */
+ if (iommupt_from_domain(domain))
+ return true;
+ return device_iommu_capable(dev, IOMMU_CAP_DEFERRED_FLUSH);
+}
+
/**
* iommu_dma_init_domain - Initialise a DMA mapping domain
* @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
@@ -706,7 +716,8 @@ static int iommu_dma_init_domain(struct iommu_domain *domain, struct device *dev
/* If the FQ fails we can simply fall back to strict mode */
if (domain->type == IOMMU_DOMAIN_DMA_FQ &&
- (!device_iommu_capable(dev, IOMMU_CAP_DEFERRED_FLUSH) || iommu_dma_init_fq(domain)))
+ (!iommu_domain_supports_fq(dev, domain) ||
+ iommu_dma_init_fq(domain)))
domain->type = IOMMU_DOMAIN_DMA;
return iova_reserve_iommu_regions(dev, domain);
diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c
index 5dca8e525c73..80b183e207e5 100644
--- a/drivers/iommu/intel/iommu.c
+++ b/drivers/iommu/intel/iommu.c
@@ -3212,8 +3212,6 @@ static bool intel_iommu_capable(struct device *dev, enum iommu_cap cap)
switch (cap) {
case IOMMU_CAP_CACHE_COHERENCY:
- case IOMMU_CAP_DEFERRED_FLUSH:
- return true;
case IOMMU_CAP_PRE_BOOT_PROTECTION:
return dmar_platform_optin();
case IOMMU_CAP_ENFORCE_CACHE_COHERENCY: