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// SPDX-License-Identifier: GPL-2.0-only
/*
* Samsung Exynos ACPM protocol based clock driver.
*
* Copyright 2025 Linaro Ltd.
*/
#include <linux/array_size.h>
#include <linux/clk-provider.h>
#include <linux/container_of.h>
#include <linux/device/devres.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/firmware/samsung/exynos-acpm-protocol.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/types.h>
struct acpm_clk {
u32 id;
struct clk_hw hw;
unsigned int mbox_chan_id;
struct acpm_handle *handle;
const struct acpm_clk_driver_data *drv_data;
};
struct acpm_clk_variant {
const char *name;
};
struct acpm_clk_driver_data {
const struct acpm_clk_variant *clks;
unsigned int nr_clks;
unsigned int mbox_chan_id;
/* For SoCs where ACPM firmware doesn't implement get_rate call */
unsigned long (*get_rate)(struct clk_hw *clk, unsigned long parent_rate);
};
#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw)
#define ACPM_CLK(cname) \
{ \
.name = cname, \
}
static const struct acpm_clk_variant exynos850_acpm_clks[] = {
ACPM_CLK("mif"),
ACPM_CLK("int"),
ACPM_CLK("cpucl0"),
ACPM_CLK("cpucl1"),
ACPM_CLK("g3d"),
ACPM_CLK("aud"),
ACPM_CLK("cam"),
ACPM_CLK("disp"),
ACPM_CLK("cp"),
};
static const struct acpm_clk_variant gs101_acpm_clks[] = {
ACPM_CLK("mif"),
ACPM_CLK("int"),
ACPM_CLK("cpucl0"),
ACPM_CLK("cpucl1"),
ACPM_CLK("cpucl2"),
ACPM_CLK("g3d"),
ACPM_CLK("g3dl2"),
ACPM_CLK("tpu"),
ACPM_CLK("intcam"),
ACPM_CLK("tnr"),
ACPM_CLK("cam"),
ACPM_CLK("mfc"),
ACPM_CLK("disp"),
ACPM_CLK("bo"),
};
static unsigned long bypass_acpm_exynos850_get_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
return parent_rate;
}
static const struct acpm_clk_driver_data acpm_clk_exynos850 = {
.clks = exynos850_acpm_clks,
.nr_clks = ARRAY_SIZE(exynos850_acpm_clks),
.mbox_chan_id = 0,
.get_rate = bypass_acpm_exynos850_get_rate,
};
static const struct acpm_clk_driver_data acpm_clk_gs101 = {
.clks = gs101_acpm_clks,
.nr_clks = ARRAY_SIZE(gs101_acpm_clks),
.mbox_chan_id = 0,
};
static unsigned long acpm_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct acpm_clk *clk = to_acpm_clk(hw);
if (clk->drv_data->get_rate)
return clk->drv_data->get_rate(hw, parent_rate);
return clk->handle->ops->dvfs.get_rate(clk->handle, clk->mbox_chan_id,
clk->id);
}
static int acpm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct acpm_clk *clk = to_acpm_clk(hw);
return clk->handle->ops->dvfs.set_rate(clk->handle, clk->mbox_chan_id,
clk->id, rate);
}
static const struct clk_ops acpm_clk_ops = {
.recalc_rate = acpm_clk_recalc_rate,
.determine_rate = clk_determine_rate_noop,
.set_rate = acpm_clk_set_rate,
};
static int acpm_clk_register(struct device *dev, struct acpm_clk *aclk,
const char *name, const struct acpm_clk_driver_data *drv_data)
{
struct clk_init_data init = {};
struct clk_parent_data pdata = {};
init.name = name;
init.ops = &acpm_clk_ops;
aclk->hw.init = &init;
/* If get_rate is set, the SoC relies on parent topology */
if (drv_data->get_rate) {
pdata.fw_name = name;
init.parent_data = &pdata;
init.num_parents = 1;
init.flags = CLK_GET_RATE_NOCACHE;
}
return devm_clk_hw_register(dev, &aclk->hw);
}
static int acpm_clk_probe(struct platform_device *pdev)
{
const struct acpm_clk_driver_data *drv_data;
const struct platform_device_id *id;
struct acpm_handle *acpm_handle;
struct clk_hw_onecell_data *clk_data;
struct clk_hw **hws;
struct device *dev = &pdev->dev;
struct acpm_clk *aclks;
unsigned int mbox_chan_id;
int i, err, count;
acpm_handle = devm_acpm_get_by_node(dev, dev->parent->of_node);
if (IS_ERR(acpm_handle))
return dev_err_probe(dev, PTR_ERR(acpm_handle),
"Failed to get acpm handle\n");
id = platform_get_device_id(pdev);
if (!id || !id->driver_data)
return -ENODEV;
drv_data = (const struct acpm_clk_driver_data *)id->driver_data;
count = drv_data->nr_clks;
mbox_chan_id = drv_data->mbox_chan_id;
clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
GFP_KERNEL);
if (!clk_data)
return -ENOMEM;
clk_data->num = count;
hws = clk_data->hws;
aclks = devm_kcalloc(dev, count, sizeof(*aclks), GFP_KERNEL);
if (!aclks)
return -ENOMEM;
for (i = 0; i < count; i++) {
struct acpm_clk *aclk = &aclks[i];
/*
* The code assumes the clock IDs start from zero,
* are sequential and do not have gaps.
*/
aclk->drv_data = drv_data;
aclk->id = i;
aclk->handle = acpm_handle;
aclk->mbox_chan_id = mbox_chan_id;
hws[i] = &aclk->hw;
err = acpm_clk_register(dev, aclk, drv_data->clks[i].name, drv_data);
if (err)
return dev_err_probe(dev, err,
"Failed to register clock\n");
}
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
clk_data);
}
static const struct platform_device_id acpm_clk_id[] = {
{ .name = "exynos850-acpm-clk", (kernel_ulong_t)&acpm_clk_exynos850 },
{ .name = "gs101-acpm-clk", (kernel_ulong_t)&acpm_clk_gs101 },
{ }
};
MODULE_DEVICE_TABLE(platform, acpm_clk_id);
static struct platform_driver acpm_clk_driver = {
.driver = {
.name = "acpm-clocks",
},
.probe = acpm_clk_probe,
.id_table = acpm_clk_id,
};
module_platform_driver(acpm_clk_driver);
MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@linaro.org>");
MODULE_DESCRIPTION("Samsung Exynos ACPM clock driver");
MODULE_LICENSE("GPL");
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