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/* SPDX-License-Identifier: GPL-2.0 */
/*
* linux/arch/arm/boot/compressed/head-xscale.S
*
* XScale specific tweaks. This is merged into head.S by the linker.
*
*/
#include <linux/linkage.h>
#include <asm/cp15.h>
.section ".start", "ax"
__XScale_start:
@ Preserve r8/r7 i.e. kernel entry values
@ set correct endianness for ixp4xx regardless of bootloader
mrc p15, 0, r0, c1, c0, 0
#ifdef CONFIG_CPU_BIG_ENDIAN
orr r0, r0, #CR_B @ enable big endian mode
#else
bic r0, r0, #CR_B
#endif
mcr p15, 0, r0, c1, c0, 0
0: mrc p15, 0, r0, c1, c0, 0
tst r0, #0x80
#ifdef CONFIG_CPU_BIG_ENDIAN
beq 0b
#else
bne 0b
#endif
sub pc, pc, #4 @ flush instruction pipeline
@ Data cache might be active.
@ Be sure to flush kernel binary out of the cache,
@ whatever state it is, before it is turned off.
@ This is done by fetching through currently executed
@ memory to be sure we hit the same cache.
bic r2, pc, #0x1f
add r3, r2, #0x10000 @ 64 kb is quite enough...
1: ldr r0, [r2], #32
teq r2, r3
bne 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
@ disabling MMU and caches
mrc p15, 0, r0, c1, c0, 0 @ read control reg
bic r0, r0, #0x05 @ clear DC, MMU
bic r0, r0, #0x1000 @ clear Icache
mcr p15, 0, r0, c1, c0, 0
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