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13 daysMerge tag 'drm-misc-next-2026-10-16' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v7.5: UAPI Changes: - Add Apple Interchange fourcc. - Expose amdxdna busy time via DRM fdinfo. Cross-subsystem Changes: - Improve DT bindings for display/ste,mcde - Add kunit test for dma_fence_dedup_array() to dma-buf/test. Core Changes: - Documentation updates to drm/scheduler, gpu/buddy. - Fail kmapping a bo without pages. Driver Changes: - Bugfixes and improvements to panel/Raystar RFF500F-AWH-DNN, accel/ivpu, vc4, accel/amdxdna, panthor, nouveau, panfrost, panthor, accel/qaic, accel/rocket, bridge/lontium-lt8713sx, appletbdrm. - Add support for BOE Novatek NT51021, Retroid Pocket 6, Raydium RM69220 DDIC panels, Sharp LQ138P1JX61 eDP, BOE NV140FHD-N43, AUO B140HAN04.0, AUO 0x0db3, panels. - Add support for Mali-G68 to panfrost. - Add Chrontel CH7218A to bridge/simple. - Support ARGB8888 for virtio primary planes. - Improve panfrost gpu reset handling and initialization. - Add HDMI 2.0 support to rockchip/dw-hdmi-qp and improve HPD handling. - Advertise HDMI 1.2 capabilities in sun4i, bridge/adv7511, it66121 & inno-hdmi. - Advertise HDMI 1.3 capabilities in bridge/ite-6263. - Advertise HDMI 1.4 capabilities in bridge/lt9611 & rockchip/rk3066_hdmi - Switch many drivers to drm_atomic_helper_create_state in preparation for readout. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patch.msgid.link/75e7de61-048c-4fdd-9ad2-6b47b29a4863@linux.intel.com
2026-10-13drm/fourcc: Add Apple Interchange layout format modifierJames Calligeros
Apple Interchange is a tiled and compressed image layout used for buffer exchange between Apple hardware blocks. It is similar to the already-supported GPU_TILED_COMPRESSED layout. Add a format modifier for Apple Interchange so that it can be used for buffer exchange. Reviewed-by: Alyssa Rosenzweig <alyssa@rosenz.ca> Signed-off-by: James Calligeros <jcalligeros99@gmail.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20261007-apple-interchange-modifier-v3-1-721fc44abf6b@gmail.com
2026-10-13Merge tag 'drm-rust-next-2026-10-11' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/rust/kernel into drm-next DRM Rust changes for v7.4-rc1 - Cross-subsystem: - I/O (shared from driver-core tree via signed tag rust-io-7.4-rc1): - Reimplement register!() as a procedural macro, require matching base types for register access, and replace relative registers with typed I/O projections. Convert Nova, Tyr and the PCI sample - Add AsRepr/AsReprMut conversions for I/O on compatible wrapper types and transmute helpers with deferred size checks - DMA (shared from driver-core tree via signed tag rust-dma-7.4-rc1): - Tie Coherent, CoherentBox and CoherentHandle to the device's bound lifetime, and allow scoped debugfs files backed by non-'static data - Allow auxiliary registration-data closures to return covariant sub-fields and add UserSliceWriter::write_truncated() - Implement Send and Sync for MapleTree - Add PCI resource_flags() and IORESOURCE_MEM_64, and convert PCI IRQ flags to impl_flags!() - Add I/O view cast() with compile-time size and alignment checks - DRM: - Add Rust dma_fence abstractions with separate producer (DriverFence) and consumer (Fence) types, per-context sequencing, signal callbacks and preallocation. Additional backend operations remain follow-up work. - Initialize DRM registrations and their data in place, removing a separate allocation - Drop the unused flags argument from drm::Registration::new() - Nova: - UAPI and Cross Module API: - Add NovaCoreApi and a lifetime-bound handle for auxiliary child drivers, carried in nova-drm registration data - Expose a render node and extensible INFO ioctl reporting GPU architecture, opaque chip ID, usable VRAM and VRAM BAR sizes, full and short GPU names, and GID, with size discovery and truncation to the userspace buffer size - Move BAR-size queries into GPU info, removing GETPARAM and changing the UAPI - PRAMIN access: - Add typed CPU access to VRAM through the movable 1 MiB BAR0 PRAMIN window, with per-architecture support from Turing through Blackwell - Add GpuMm centralized memory manager, VramAddress type, aperture documentation and optional probe-time self-tests under CONFIG_NOVA_CORE_SELFTESTS - GPU virtual memory and BAR1: - Add VRAM buddy allocation, TLB flushing, MMU v2/v3 page-table types with trait-based generics (PteOps, PdeOps, DualPdeOps, MmuConfig) and a generic walker - Add maple-tree virtual address tracking and multi-page mapping, separating allocation from mapping execution - Add CPU access to mapped VRAM through BAR1 and memory-management self-tests; handle 64-bit BAR0 when locating BAR1 - GPU interrupts and GSP events: - Add GIN (GPU Interrupt and Notification) interrupt-tree support with MSI-X, MSI fallback and per-architecture rearming - Drain GSP events between commands via a threaded SWGEN0 handler - Report OS errors, robust-channel notifications and unknown messages without aborting command waits; hold the queue lock and use one deadline per wait - Disable GSP event interrupts on persistent falcon faults or drain errors - Add a delivery/rearm self-test, interrupt-tree KUnit coverage and interrupt-controller documentation - GSP messaging fixes: - Queue setup RPCs before GSP-RM boot - Correct DMA barriers in both queue directions - Firmware and transport: - Extract a reusable radix3 buffer mapper; zero-pad page-table levels to whole pages to prevent booter reads of stale padding - Correct GSP-FMC naming and boot-flow documentation - Set MCTP header version 1 for FSP messages and retain the command queue's BAR0 reference - Resource handling: - Replace unnecessary BarUser reference counting with in-place ownership and borrowed access; consolidate probe initialization - Declare an unlimited DMA maximum segment size - Tyr: - Use bitfield!() for firmware section flags and memory attributes that do not describe registers - Zero unsupported and newly added GPU-info fields, and limit the doorbell array to 17 entries to fit the mapped register region Signed-off-by: Dave Airlie <airlied@redhat.com> From: "Danilo Krummrich" <dakr@kernel.org> Link: https://patch.msgid.link/DM371PN4TBJT.3LY1B0EYWSI4@kernel.org
2026-10-12drm/panfrost: Fix races between perfcnt and reset sequenceAdrián Larumbe
Formerly, the reset sequence would race with panfrost_mmu_as_put() when tearing down a perfcnt session. On top of that, poking GPU registers to program a perfcnt session or obtaining a dump might lead to undefined behaviour when done at the same time a reset was ongoing. Use the reset r/w semaphore when disabling and re-enabling perfcnt configuration, and also in the sections inside the 'enable'and 'dump' ioctls where device registers are being accessed. On top of that, expand the DRM uAPI for the perfcnt DUMP operation so that user space can be made aware of a reset having happened, whether it succeeded or failed to restore the original configuration. UM needs to know about this condition because counter data is inaccurate after a reset, so the best approach might be simply to try again. Finally, update driver uAPI documentation to explain the meaning of the new perfcnt dump ioctl's state flags, and bump DRM driver minor number to reflect the new DUMP IOCTL req field. Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Fixes: 73e467f60acd ("drm/panfrost: Consolidate reset handling") Fixes: 7786fd108777 ("drm/panfrost: Expose performance counters through unstable ioctls") Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20261012-claude-fixes-v15-15-bc0a6c498553@collabora.com Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com>
2026-10-11Merge tag 'amd-drm-next-7.4-2026-10-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-10-08: amdgpu: - Fix direct scanout alpha on some DRM_FORMATs - UserQ fixes - Fix for PSR with tearing flips - GPU reset vblank fix - Debugfs register interface fix - Fix mode patching - Expand Mac reserved memory workaround - GC 12.1 fixes - Clean up MES/HWS vmid mask handling - Make runtime pm more fine grained - A+A SPM fixes - SR-IOV fixes - 3D LUT fixes - HDMI fixes - DCN 4.2 fixes - HDMI VRR fixes - DC tracing fixes - UALink fixes amdkfd: - SDMA doorbell fix - Fix dma-buf reference leak in error path Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20261008212310.2508510-1-alexander.deucher@amd.com
2026-10-05drm: nova: Move VRAM BAR size query to GPU infoDanilo Krummrich
Nova exposes static information via its DRM_IOCTL_NOVA_INFO ioctl, thus add vram_bar_size to struct drm_nova_info_gpu and remove DRM_IOCTL_NOVA_GETPARAM and its uAPI definitions. This breaks the uAPI, which is still fine at this point. It requires the corresponding drm-test change in [1]. Link: https://gitlab.freedesktop.org/dakr/drm-test/-/merge_requests/2 [1] Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Reviewed-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260927142258.1260711-1-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-10-02drm/tegra: Wait for syncpoint syncobj_in fences in hardwareMikko Perttunen
Currently all syncobj_in fences are waited synchronously on the CPU. However, since Host1x channels are capable of waiting for syncpoint fences on the hardware, let's use that capability. This filters the any non-syncpoint (or different host1x instance) fences in syncobj_in, waits only those on the CPU, and adds the rest as waits to the channel before the actual job contents. Also make minor clarifications to the doc comments in the UAPI header. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20260730-b4-host1x-syncobj-wait-v1-6-afa730410392@nvidia.com
2026-10-01drm/amdgpu: support MP5 in firmware info queriesYang Wang
Handle AMDGPU_INFO_FW_MP5 in the firmware query path and report the MP5 firmware version in the debugfs firmware_info output. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-27drm: nova: Report GPU GID in GPU infoAlistair Popple
Add the GPU GID to the reported GPU info. This is the 16-byte SHA-1 based identifier GSP-RM reports for the GPU. Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-14-apopple@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Report GPU short name in GPU infoAlistair Popple
Add the short GPU name to the GPU info structure. As with the full name it is copied from a validated, NUL-terminated string extracted by nova-core rather than from the raw firmware bytes. Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-13-apopple@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Report GPU name in GPU infoAlistair Popple
Add the full GPU name to the GPU info structure. The name is copied from the validated, NUL-terminated string nova-core already extracts from the GSP static info rather than from the raw firmware bytes. GpuInfo::new() is deliberately fallible here. A malformed name string from the GSP is unexpected and is reported to userspace as an error rather than being silently replaced with an empty name. Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-12-apopple@nvidia.com [ Use ..pin_init::zeroed() instead of ..default::Default(). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Add usable VRAM size to GPU infoAlistair Popple
Add a field to the GPU info structure containing the total usable framebuffer size. The usable framebuffer excludes GSP carveouts and other protected regions, so it may differ from the BAR size and total physical VRAM. Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-9-apopple@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Add an info ioctlAlistair Popple
Add an extensible info ioctl and use it to report basic GPU information. One of the first things userspace needs to know about a GPU is its architecture and which chip it is, so add those as the first fields in the GPU info result. The chip identifier is opaque to userspace and is only meaningful when compared against the values of enum drm_nova_chipid. The ioctl selects an information type by ID and writes the result through a sized userspace buffer. The kernel truncates results to the supplied size, allowing information structures to grow and new logical information groups to be added without introducing new ioctls. Passing a NULL data pointer returns the size of the requested information structure instead. Suggested-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-8-apopple@nvidia.com [ Avoid 'as' casts (add From<Chipset> for u32, From<Architecture> for u32 and use IntoSafeCast, IntoSafeCastArch); improve / simplify a few comments. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Add chipid enum to nova-drm UAPIAlistair Popple
The chip identifier uniquely identifies a GPU chip and needs to be exposed to user-space so it can look up chip specific properties that cannot be derived from the architecture alone. This adds a public enum to the userspace headers for each chip ID. Nova-core can then use this enum to define its chipsets. The values are opaque to user-space. They may be compared against the enum to identify a chip but user-space must not assume the values carry any particular meaning or encoding. This does create a coupling between nova-drm and nova-core whereby nova-core depends on the values defined by the user-space API for nova-drm. However this is entirely appropriate as nova-core must be bound by the UAPI headers as the enum values are read by nova-core and passed through to user-space. Note that nova-core currently refers to the chipid as a chipset. This isn't ideal given that chipid is the preferred and more accurate term and is what should be exposed via the uAPI. Therefore a future patch series will be posted that aligns nova-core internals to using chipid rather than chipset. Assisted-by: LLM Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-6-apopple@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-27drm: nova: Add GPU architecture enum to nova-drm UAPIAlistair Popple
The GPU architecture to be exposed to user-space. This adds a public enum to the userspace headers for each chip architecture. Nova-core can then use this enum to define its architectures. This does create a coupling between nova-drm and nova-core whereby nova-core depends on the values defined by the user-space API for nova-drm. However this is entirely appropriate as nova-core must be bound by the UAPI headers as the enum values are read by nova-core and passed through to user-space. It also requires a minor change to the bounded_enum! macro to match the architecture values in an expression context. Signed-off-by: Alistair Popple <apopple@nvidia.com> Link: https://patch.msgid.link/20260909064506.910162-5-apopple@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-09-22Merge tag 'drm-xe-next-2026-09-18' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - Add SRCID to pagefault reporting (Jonathan) Cross-subsystem Changes: - gpusvm: share one HMM fault and keep single mappings inline (Honglei) - pagemap: Prevent CPU stalls during unbounded pagemap teardown (Varun) Driver Changes: - VRAM health check + CCS fix (Auld) - Add memory page offlining support (Tejas) - Report GT TDR and VM rebind faults using SIGID (Arvind) - Flush LSC untyped L1 dataport cache after rcs/ccs batches (Thomas) - Add multi_queue_active_lrca debugfs (Varun) - mmio_gem: fix fault handler and destroy path (Auld, Ilia, Shuicheng) - sysctrl: Add helper to query application status (Anoop) - shrinker: Runtime PM reference for non-system memory (Shuicheng) - pcode: Increase default mailbox timeout (Karthik) - Skip clearing purged page-table BOs (Tejas) - tests: Fix subplatform selection (Wajdeczko) - log: Relax location ID recognition (Wajdeczko) - i2c: Disable IRQ on unbind (Raag) - Refactor VF LMEM BAR resize helper function (Wajdeczko) - pf: Add _locked variant of config functions (Wajdeczko) - nvm: add system controller region (Alexander) - guc: Add simple KLV decoder helpers (Wajdeczko) - debugfs: Expose per-engine idle status (Anirban) - gt_throttle: Report power brake as a throttle reason on CRI (Anirban) - tlb_inval: Treat wedged-device invalidations as complete (Shuicheng) - Add mnemonic error reason to page fault diagnostics (Brost) - Keep walking on SVM eviction failure (Brost) - Make p2pdma distance check verbose via dynamic debug (Thomas) - Consolidate semaphore instruction definitions (Roper) - Poll GT for C6 before D3 (Vinay) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/aq2UzTdN95ZpzKGz@gsse-cloud1.jf.intel.com
2026-09-18Merge tag 'drm-misc-next-2026-09-17' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v7.4: UAPI Changes: ivpu: - add DRM_IVPU_CAP_CMDQ_SET_PRIORITY Cross-subsystem Changes: dma-fence: - fix documentation vga_switcheroo: - disconnect from fbcon; update fbcon from within DRM fbdev emulation Core Changes: atomic: - replace state reset callback with create_state throughout DRM core and drivers panic: - split into core and helpers sched: - clean up interface sysfs: - drop drm_class_device_register() Driver Changes: amdxdna: - fix BO handling arcpgu: - replace simple-display pipeline with regular atomic helpers aspeed: - replace simple-display pipeline with regular atomic helpers gm12u320: - replace simple-display pipeline with regular atomic helpers imagination: - various improvement to firmware interaction ivpu: - support command-queue priority ioctl mcde: - replace simple-display pipeline with regular atomic helpers p111: - replace simple-display pipeline with regular atomic helpers - drop unsupported alpha formats from primary plane panel: - edp: Add support for BOE NV140FHM-T0A - samsung: Share test-key helpers rcar-du: - support Renesas R-Car V4H DSC - dsi: Support larger transfers with AXI memory repaper: - replace simple-display pipeline with regular atomic helpers rockchip: - dsi: improve PHY timings ssd130x: - support Solomon SSD1351 OLED plus DT bindings - ssd133x: upgrade color format to RGB565 tve200: - replace simple-display pipeline with regular atomic helpers xen: - replace simple-display pipeline with regular atomic helpers Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260917090534.GA420415@2a02-2455-9062-2500-ec39-e8a6-193-9c05.dyn6.pyur.net
2026-09-17Merge tag 'amd-drm-next-7.4-2026-09-10' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-09-10: amdgpu: - Freesync fixes - GPUVM fix - Debugfs fixes - HDMI updates - IPS fix - GPU reset fix - RGB quantization fixes - SMU 13.0.x fixes - MES updates - UserQ updates - UVD fix - Various bounds checks - DML fixes - DCN 6 updates - NBIO 7.11.5 support - Audio fixes - More display KUnit tests - SMU 15 updates - RAS updates - VCN 5.0.2 updates - JPEG 5.0.2 updates - DCN 4.2 updates - PSR fixes - Misc cleanups - PSP 15.0.8 updates - RAS BERT support - RAS CPER updates - vblank fixes - LSDMA updates - GC 12.1 updates - MMHUB 4.2 updates - NBIO 6.3.2 updates - SMU 15.0.8 updates - IP discovery updates - GPU spatial partitioning updates - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - Require jobs for IBs - Enable FRL for HDMI - MES oversubscription fixes - IH 6-7 updates - GMC 11-12 fault handling updates - Fixed point cleanup - Backlight fixes - GPUVM cleanup - Devcoredump fixes - UALoE (UALink over Ethernet) Support - SDMA userq fixes - GC 8 fix amdkfd: - Various bounds checks - SVM fixes - GC 12.1 updates - MES updates - Trap handler fixes - Debugfs fixes drm: - Add gem callback for when handle count goes to 0 - Rust fix UAPI: - INFO IOCTL fix for 32 bit userspace on 64 bit kernel - Add syncobj_points to USERQ signal ioctl Proposed userspace: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 - Add UALink support IOCTLs Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260910213040.826425-1-alexander.deucher@amd.com
2026-09-11accel/ivpu: Add support for getting and setting command queue priorityAndrzej Kacprowski
Add a new DRM_IVPU_PARAM_CMDQ_PRIORITY parameter to query and update the scheduling priority of an existing command queue, identified by its ID via drm_ivpu_param.index. The priority can be changed on a queue that already has pending jobs; if the queue's doorbell is registered, the new priority is propagated to the firmware immediately, otherwise it is applied when the queue is next registered. The firmware picks up the change at the first opportunity. The feature requires HW scheduling mode and is advertised through the new DRM_IVPU_CAP_CMDQ_SET_PRIORITY capability. Legacy command queues are not supported. Signed-off-by: Andrzej Kacprowski <andrzej.kacprowski@linux.intel.com> Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Link: https://patch.msgid.link/20260831121617.395523-1-andrzej.kacprowski@linux.intel.com
2026-09-08Merge tag 'drm-misc-next-2026-09-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v7.4: UAPI Changes: colorop: - provide DRM_COLOR_OP_FIXED_MATRIX Cross-subsystem Changes: cgroups: - fix typos dma-buf: - fix typos sound: - adapt to changes in omapdrm Core Changes: atomic: - convert most of DRM from state reset callbacks to atomic_create_state - remove drm_simple_encoder_init(); update drivers buddy: - improve dirty-page tracking clients: - log: Improve vmap handling display: - export HDMI SCDC status data via debugfs edid: - parse AMD VSDB entries - parse ALLM/VRR capabilities log: - add drm_warn_ratelimited() sched: - add missing locking Driver Changes: amd: - display: Use AMD VSDB for FreeSync - display: Implement YUV-to-RGB with fixed-matrix colorop amdxdma: - various fixes ast: - support 256-byte EDID data bridge: - clean up redundant error reporting - ti-sn65dsi83: Simplify error condition logic hyperv_drm: - remove support for pre-Win10 hosts komeda: - fix usage of GLB_CORE_ID nouveau: - improve runtime PM on R570 GSP firmware - various fixes throughout the driver - dispnv50: Support 2.147 GHz pixel clock in GB20x omap: - report HDMI hotplug events to ASoC HDMI codec panel: - panel-edp: Support MNE007QS3-F, TM140VDXP15, and KD116N36-30NB-A001 - samsung-s6d16d0: Use mipi_dsi_*_multi() functions - support Ilitek ILI7836A OLED plus DT bindings - support Novatek NT36532 plus DT bindings - convert several drivers to managed cleanup - fix Kconfig selections panthor: - provide gpu_cache_flush tracepoint - improve dma_fence signalling latency - improve locking qaic: - reject BOs that exceed maximum page count - add missing include statements verisilicon: - fix hardware cursor offsets vkms: - implement YUV-to-RGB with fixed-matrix colorop Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20260903130548.GA91506@2a02-2455-9062-2500-3419-2212-e55c-8a45.dyn6.pyur.net
2026-09-08Merge tag 'drm-xe-next-2026-08-31-1' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next Cross-subsystem Changes: - MAINTAINERS: Add entries for drm_ras (Rodrigo) - alerts and controller enabling modifications (Heikki) Core Changes: - Introduce cold reset recovery method (Mallesh) - Add drm_ras netlink error event support (Riana) - Introduce error threshold to drm_ras (Raag) Driver Changes: - Remove sysfs entry on idr_alloc failure in xe_oa_add_config_ioctl (Lu) - match argument naming with PCODE_DATAx (Grzelak) - fix stale GGTT mappings on unmap (Tangudu) - Introduce error threshold to drm_ras (Raag) - Add debugfs knob to control GPGPU preemption granularity (Varun) - fix vecs config for powergating info (Ashutosh) - Read mailbox phase bit from hardware (Anoop) - alerts and controller enabling modifications (Heikki) - Use int instead of u32 for mailbox status (Umesh) - Reject page faults from non-fault-mode scratch VMs (Arvind) - Add CCS to the powergating info print (Balasubramani) - Do not apply WA 14025883347 to media 3503 (Daniele) - don't WARN on kernel job timeout when device already wedged (Nitin) - handle exec queue teardown after hot-unplug (Nitin) - Allow debugging PCI errors (Raag) - Add structured SIGID error logging infrastructure (Wajdeczko, Rodrigo) - Enable package and vram temperatures for CRI (Karthik) - Introduce cold reset recovery method (Mallesh) - fix error message in xe_migrate_sanity_test (Dan Carpenter) - Add drm_ras netlink error event support (Riana) - Fix a bug in pc_adjust_freq_bounds() (Vinay) - Fix xe_device_probe() failure (Raag) - Page fault cleanups (Wajdeczko) - OA memory fixes (Linmao) - document sentinel and make CTX_TIMESTAMP read TOCTOU-safe (Gajendra) - Move has_drm_ras check to drm_ras layer (Raag) - add termination on resume (Daniele) - Add _locked variants of some config functions (Wajdeczko) - Order ring writes before ring tail updates (Brost) - Parallel page fault handling (Brost) - handle CRI+ power interval encoding (Karthik) - allocate UM queues in a separate UC BO (Jia) - Fix boot-time ras error processing (Raag) - VF migration for multi-queue (Niranjana) - Apply RCS/CCS yield policy to SR-IOV VFs (Marcin) - Fix memory leak in exec_queue_set_hang_replay_state (Winiarski) - Use IBC v3 on PTL (Vinay) - Reduce MERT debug log spam (Lukasz, Piotr) - Validate sysctrl response (Raag) - Changes for Xe3p_HPM media (Ashutosh) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/apYbnrklyk6nNO7Q@gsse-cloud1.jf.intel.com
2026-09-07Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get drm-misc-next up to v7.3-rc2. Requested for commit 3a2c4d55e32a ("treewide: refresh kmalloc_obj() conversions"). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-09-03drm/xe/uapi: Expose ban reason in EXEC_QUEUE_GET_PROPERTY_BANTejas Upadhyay
Extend DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN to return a bitmask indicating the reason for the ban, rather than a simple boolean. This allows userspace to distinguish between different ban causes: - DRM_XE_EXEC_QUEUE_BAN_REASON_GPU_HANG (bit 0): exec queue was banned due to a GPU hang or job timeout detected by the TDR. - DRM_XE_EXEC_QUEUE_BAN_REASON_PAGE_OFFLINE (bit 1): exec queue was banned because a VRAM page backing its resources was taken offline. The ban_reason field is added to struct xe_exec_queue and set at the point where the ban is triggered: - In guc_exec_queue_timedout_job() for GPU hang. - In xe_ttm_vram_purge_page() for memory page offline, before calling xe_exec_queue_kill() or xe_vm_kill(). The reset_status op is updated to return u64 with the reason bitmask. When a queue is banned but no explicit reason was recorded (e.g., from a generic CAT error), it defaults to GPU_HANG for backward compatibility. A value of 0 means the exec queue is not banned. v5 (Sashiko/MattB): - Take the write lock for the traversal to tag ban_reason v4(Sashiko): - Add ban reason for non-LR exec queues - Add TODO for multiqueue v3(Rodrigo): - Add doc in xe_drm.h v2(Sashiko): - Use atomic_t for ban_reason to fix concurrent updates from TDR and page-offline - Guard GPU_HANG bit with !exec_queue_killed to avoid masking page-offline reason - Clear ban_reason on queue recovery (clear_exec_queue_banned path) - Use atomic_read in guc_exec_queue_reset_status for lockless read Assisted-by: Copilot:claude-opus-4.6 Acked-by: José Roberto de Souza <jose.souza@intel.com> Acked-by: Michal Mrozek <michal.mrozek@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260903161553.528932-31-tejas.upadhyay@intel.com
2026-09-03drm/xe/vm: Add srcid to xe_vm_get_property_ioctl fault reportJonathan Cavitt
Add the SRCID of the faulting hardware unit to the return of the xe_vm_get_property_ioctl fault report. v2: - Readd pad check, as the pad in the ioctl struct was not changed (jcavitt) v3: - Squash SRCID with ASID to keep the struct compact (Matthew) Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Reviewed-by: Matthew Brost <matthew.brost@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: David Airlie <airlied@gmail.com> Cc: Simona Vetter <simona@ffwll.ch> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Maxime Ripard <mripard@kernel.org> Cc: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Matthew Brost <matthew.brost@intel.com> Link: https://patch.msgid.link/20260902214358.348399-3-jonathan.cavitt@intel.com
2026-09-02drm/amdgpu/userq: fix struct drm_amdgpu_info_device padding for 32bit compileYogesh Mohan Marimuthu
need to pad before __u64 tcc_disabled_mask variable. This patch fixes 64bit Kernel + 32 bit mesa combination. But at the same time it will break 32bit Kernel(using this patch) + older 32bit mesa(not using this patch). This issue was discussd with alexander.deucher@amd.com, christian.koenig@amd.com and pierre-eric.pelloux-prayer@amd.com. Currently today 32 bit kernel + 32 bit userspace and 64 bit kernel and 64 bit userspace work. Mixed 64 bit kernel and 32 bit userspace is currently broken. Since 32 bit kernel and userspace is probably pretty rare these days and the data affected by this is not critical, Hence we can go ahead with this patch. Fixes: cf21e76a6005 ("drm/amdgpu: return tcc_disabled_mask to userspace") Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 497b5090f2857ef8ad9a162aa31ada0de5814663)
2026-09-02drm/amdgpu: Add ioctl infra for exporting/importing UALink handlesMukul Joshi
Add the ioctl infrastructure to support exporting and importing BOs to facilitate NPA based memory sharing across GPUs in a rack scale setup. Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 v2: Move the ioctl wire-up to the end of the series. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Signed-off-by: Horatio Zhang <hongkun.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amdgpu: Add a new NPA Address spaceMukul Joshi
Add a new address space for NPA address management. This is needed for sharing buffer objects across GPUs with each running their own OS. The NPA address space size can change across different HW generations so the size is initialized during early init of the driver boot up process. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-02drm/amdgpu/userq: fix struct drm_amdgpu_info_device padding for 32bit compileYogesh Mohan Marimuthu
need to pad before __u64 tcc_disabled_mask variable. This patch fixes 64bit Kernel + 32 bit mesa combination. But at the same time it will break 32bit Kernel(using this patch) + older 32bit mesa(not using this patch). This issue was discussd with alexander.deucher@amd.com, christian.koenig@amd.com and pierre-eric.pelloux-prayer@amd.com. Currently today 32 bit kernel + 32 bit userspace and 64 bit kernel and 64 bit userspace work. Mixed 64 bit kernel and 32 bit userspace is currently broken. Since 32 bit kernel and userspace is probably pretty rare these days and the data affected by this is not critical, Hence we can go ahead with this patch. Fixes: cf21e76a6005 ("drm/amdgpu: return tcc_disabled_mask to userspace") Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-31Merge drm/drm-next into drm-xe-nextMatthew Brost
Prep drm-xe-next for 7.4 PR. Signed-off-by: Matthew Brost <matthew.brost@intel.com>
2026-08-31Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Getting drm-misc-next up to v7.3-rc1. In exynos, there was a conflict in exynos_dbi_bind(). The merge resolves it to the state of commit 3cc8eee9f346 ("drm/exynos: remove dependency on DRM simple helpers"). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-08-28drm/ras: Introduce error thresholdRaag Jadav
Add get-error-threshold and set-error-threshold command support which allows querying/setting error threshold of the counter. Threshold in RAS context means the number of errors the hardware is expected to accumulate before it raises them to software. This is to have a fine grained control over error notifications that are raised by the hardware. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Riana Tauro <riana.tauro@intel.com> Acked-by: Joshua Santhosh Ranjan <joshua.santosh.ranjan@intel.com> Link: https://patch.msgid.link/20260818135304.497098-3-raag.jadav@intel.com Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-08-27drm/colorop: Add DRM_COLOROP_FIXED_MATRIXChaitanya Kumar Borah
Introduce DRM_COLOROP_FIXED_MATRIX, a new colorop type representing a hardware that performs a fixed matrix operation. Unlike CTM-based colorops, this block does not expose programmable coefficients. Instead, userspace selects one of the predefined hardware modes via a new FIXED_MATRIX_TYPE enum property. Supported modes include common YCbCr->RGB and RGB709->RGB2020 conversions. v5: - Drop YCbCr limited to full and RGB709 to RGB2020 matrices until we have non-IGT userspace that shows their use (Robert) v4: - Add limited-range YCbCr-RGB conversion matrix enums (Robert) - Document matrix values (Pekka) - Clarify RGB709 to RGB2020 is a full-range matrix (Pekka) - Fix confusing "CSC preset" doc (Pekka) v2: - Naming changes (Pekka) v3: - Fix NC matrix enum name and string (Melissa) - Rebase Co-developed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Melissa Wen <mwen@igalia.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Robert Mader <robert.mader@collabora.com> Reviewed-by: Alex Hung <alex.hung@amd.com> Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com> Link: https://patch.msgid.link/20260814211816.1219597-2-harry.wentland@amd.com
2026-08-25drm/amdgpu/userq: Add syncobj_points to signal ioctlDavid Rosca
Userspace patches: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 Signed-off-by: David Rosca <david.rosca@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-24Merge tag 'drm-msm-next-2026-08-01' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-next Changes for v7.3 Bindings: - Added Shikra support - Document a840, a704, a722 Core: - Use drm_client buffers for fbdev emulation - teardown fixes - ARM32 DMA fixup - Remove objects from evict list when re-validated - Bunch of corner case and error path fixes DPU: - Dropped dev_pm_opp_set_rate(0) preventing burnout - Fixed SSPP offsets of Kaanapali DP: - Dropped dev_pm_opp_set_rate(0) preventing burnout - Cleaned up core code in preparation for MST support - Fixed prepare() to let Pipewire continue in case of the unplugged cable GPU: - Add support for a704 - Add support for a722 HDMI: - Simplifed register access Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <rob.clark@oss.qualcomm.com> Link: https://patch.msgid.link/CACSVV02Kp=J+w_RjEJbBbQnBYRb+SWdwMvVbCaAL70bq9EBagQ@mail.gmail.com
2026-08-12drm/drm_ras: Add drm_ras netlink error eventRiana Tauro
Define a new netlink event 'error-event' and a new multicast group 'error-report' in drm_ras. Each event contains device name, node and error information to identify the error triggering the event. Add drm_ras_nl_error_event() to trigger an event from the driver. Userspace must subscribe to 'error-report' to receive 'error-event' notifications. Usage: $ sudo ynl --family drm_ras --subscribe error-report Cc: Jakub Kicinski <kuba@kernel.org> Cc: Zack McKevitt <zachary.mckevitt@oss.qualcomm.com> Cc: Lijo Lazar <lijo.lazar@amd.com> Cc: Hawking Zhang <Hawking.Zhang@amd.com> Cc: David S. Miller <davem@davemloft.net> Cc: Paolo Abeni <pabeni@redhat.com> Cc: Eric Dumazet <edumazet@google.com> Signed-off-by: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Link: https://patch.msgid.link/20260810112008.1858731-5-riana.tauro@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-08-08Merge tag 'drm-misc-next-2026-08-06' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v7.3: UAPI Changes: - Remove the default udmabuf size limit of 64MB. Cross-subsystem Changes: - Add dmemcg support for eviction, and hook it up for amdgpu and xe. Core Changes: - Changes to TTM to be more aggressive when allocating below protection limit! - Improve dt binding documentation for renesas. - Add helper to convert physical address back to buddy block, add that to and improve its kunit test. Driver Changes: - Assorted small fixes to ti-sn65dsi86, panthor, imagination, omapdrm, bridge/synopsys, panel-edp, ssd130x, panel/tdo-tl070wsh30. - Add Sharp LQ120P1JX51 panel. - Add dmemcg support to nouveau. - Various updates and improvements to sun4i, among which YUV and 4k support. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patch.msgid.link/917d462a-8976-4a15-bec4-4513ec51c5c0@linux.intel.com
2026-08-01Merge tag 'drm-xe-next-2026-07-30' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next - Wait on external BO kernel fences in exec IOCTL (Brost) - General clean-up (Anas) - Documentation fix (Rafael) - Add a debugfs for pcode information (Karthik) - Free madvise VMA array on L2 flush failure (Guangshuo) - Page Table related fixes (Shuicheng, Zongyao) - Improvements GuC error handling and GuC small fixes (Sk, Zhanjun, Arvind) - Add new W/As (Daniele, Harish) - GuC paging engine support (Auld) - Add and use more KLV helpers (Michal) - Balance exec queue suspend/resume (Niranjana, Thomas) - Fix BO prefetch with CONSULT_MEM_ADVISE_PREF_LOC (Himal) - SRIOV: Disable display in admin only PF mode (Satya) - Fix writable override for CRI NVM (Sasha) - Fix VF CCS attach/detach race with in-flight BO moves (Brost) - Introduce Xe Uncorrectable Error Handling (Riana) - Fix WOPCM size for LNL+ (Daniele) - Consolidate debugfs fault injection functions (Mallesh) - Multi-queue related fixes and improvements (Niranjana, Jagmeet, Shuicheng) - Add RAS GPU health indicator (Soham) - PAT related improvements (Roper, Sanjay) - NULL deref fix on migration on VF (Satya) - i2c related fix (Raag) - Fix SVM leak and clean up xe_vm_create (Shuicheng) - Drop force_probe requirement for NVL-s (Gustavo) - Optimise TT population for DONTNEED BOs (Auld) - Add page size allocation mode control and coverage (Himal, Nareshkumar) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/amt2kDVdyBK6VEyU@intel.com
2026-07-28drm/fourcc: Add modifiers for AMD GFX6-8Timur Kristóf
GFX6-8 are the oldest GPUs supported by the amdgpu kernel driver, and the last ones that didn't support DRM format modifiers until now. These are the Southern Islands, Sea Islands and Volcanic Islands families of GPUs. On GFX6-8, the GFX block can only use pre-determined tiling modes which are programmed by the kernel according to the tiling mode table. GFX6 uses the GB_TILE_MODE0...31 registers, and GFX7-8 also has GB_MACROTILE_MODE0...15 registers. DCC is also supported on GFX8, albeit not displayable. Note that the tiling table is uAPI and userspace relies on specific modes being present at specific indices. How the tiling works is primarily determined by the so-called array mode. Use the TILE field to specify the array mode. Pixel data is organized into micro tiles. Each micro tile may be 8x8 / 8x8x4 / 8x8x8 pixels, depending on the array mode. Add the MICROTILE field to specify microtile mode. Microtiles may be further organized into macro tiles, which have many configurable parameters. Macro tile mode selection depends on how many bits per pixel an image has. Add the PIPE_CONFIG, TILE_SPLIT, BANK_WIDTH, BANK_HEIGHT, MACRO_TILE_ASPECT, NUM_BANKS fields to specify parameters of macro tiled modes. Furthermore, tiling is also influenced by memory configuration. Old RFC patches received feedback concerning that, so I looked into it specifically: GB_ADDR_CONFIG.ROW_SIZE needs to be considered when calculating TILE_SPLIT, but does not need to be included in the modifiers, and also PIPE_INTERLEAVE matters, but it's hardcoded to the same value on all GFX6-8 GPUs and changing it would break userspace, so let's assume it isn't going to change. Therefore we don't need to include that in modifiers. Mesa also reads NUM_RANKS but actually doesn't use its value on GFX6-8. As a side note, tiling works similarly on GFX4-5 (that is Evergreen and Northern Islands). But that will need some additional PIPE_CONFIG enum values as well as some extra fields not relevant to GFX6-8. Initially, let's only expose the tiling modes that are most relevant to sharing buffers between different processes: Exposed array modes (TILE field): - 1D_TILED_THIN1: micro tiled only - 2D_TILED_THIN1: macro tiled Exposed micro tile modes (MICROTILE field): - DISPLAY: supported by DCE (the display engine) - THIN: more efficient but not displayable Exposed macro tile modes: All possible parameters (25088 permutations). More modes may be exposed in the future as needed. Technically, the amount of possible combinations of all possible tiling parameters is in the range of hundreds of thousands, but in practice, there are just a handful of possible modifiers for a surface. For example on GFX8, a surface would have these modifiers, from best to worst performance: - 2D_TILED_THIN1 + THIN + DCC + macrotile params [1] - 2D_TILED_THIN1 + THIN + macrotile params [1] - 2D_TILED_THIN1 + DISPLAY + macrotile params [1] - 1D_TILED_THIN1 + THIN - 1D_TILED_THIN1 + DISPLAY - LINEAR [1] The macro tiling parameters depend on how many bits per pixel of the specific surface has and how the chip is configured. There is only one set of valid macrotile params for a given surface. DCC is only supported by GFX8 and newer, and only with non-displayable macrotiling modes. When sharing buffers between different GFX6-8 GPUs, it is very unlikely that they support the exact same macrotiling configuration, so they will likely need to use micro tiled modes, which are still much better than using linear buffers. (Note that currently Mesa always uses LINEAR when copying between two GPUs.) Suggested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Daniel Stone <daniels@collabora.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-07-28drm/msm: Fix stale comments in uapi/drm/msm_drm.hHans de Goede
At some point drm_msm_gem_syncobj was renamed to drm_msm_syncobj and MSM_SUBMIT_SYNCOBJ_FLAGS was renamed to MSM_SYNCOBJ_FLAGS but some comments still refer to the old names. Update the comments with the new names. Signed-off-by: Hans de Goede <johannes.goede@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/742717/ Message-ID: <20260728092609.22049-1-johannes.goede@oss.qualcomm.com> Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
2026-07-27drm/nouveau: allow allocating NVDEC channels via abi16Dave Airlie
Add NOUVEAU_FIFO_ENGINE_NVDEC to the abi16 uAPI and accept it in channel allocation, mapping it to the NVDEC engine runlist. Skip the Turing copy-engine workaround object for NVDEC channels: the copy engines are not part of the NVDEC runlist, so the workaround object cannot be instantiated on such channels (and is not needed there). This is required for NVK to implement Vulkan Video H.264 decode on top of the NVDEC engine: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31867 Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com> Signed-off-by: Dave Airlie <airlied@redhat.com> Link: https://patch.msgid.link/20260725035912.1016464-1-daniel.almeida@collabora.com
2026-07-14Merge drm/drm-next into drm-xe-nextRodrigo Vivi
Sync some i915/display changes Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2026-07-07Merge tag 'amd-drm-next-7.3-2026-07-02' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next [airlied: had to reapply drm/amdgpu: Implement "color format" DRM property by hand to amdgpu_dm_connector.c] amd-drm-next-7.3-2026-07-02: amdgpu: - Queue reset updates - Initial compute pipe reset support - Improved boundary checking for bios parsing - Cleaned up sysfs input parsing - devcoredump fixes - RAS updates and rework - VCN secure submission fixes - 8K panel fix - Add display KUnit tests - Display CRC fixes - UserQ updates - Backlight fixes - Parse panel type info from DisplayID - Align IP discovery to pci device lifetime - IOCTL boundary check fixes - Convert amdgpu_vm_lock_by_pasid() to drm_exec - Ctx fixes and cleanup - SOC15 register macro cleanups - Memory placement fixes for UVD - Disable KQ support for MI3xx - GFX9 mode2 reset fix - BO list cleanup - Soc24 aborted suspend fix - Gfx8 soft reset rework - Enable soft reset on gfx8 - Drop unnecessary BUG() and BUG_ON() in error paths - Fix power reporting unit conversion - Improve vbios command table bounds checking - UVD bounds checking improvements - VCN bounds checking improvements - PSR and replay fixes - DCN 4.2 updates - Colorop updates - DC GPIO rework - ACP fixes - Fix aperture mapping leak - Ignore_damage_clips fix - Fixes for non-4K pages - JPEG idle check fixes - Userptr fixes - GPUVM fixes - GC 11.7 updates - SMU 13 fixes amdkfd: - Initial compute pipe reset support - Allow applications to opt out of sigbus on fatal errors - Fix doorbell/mmio BO cleanup - Improved CRIU boundary checking - MQD handling rework - SMI fixes - Reset event fixes - CRIU fixes - Sysfs teardown fixes - IOCTL boundary check fixes - SVM fixes - Soft IH ring fixes - Move TBA/TMA from system to device memory radeon: - Blit fix for large BOs - r600 dpm cleanup fix drm: - Extract EDID base section header processing into helper - Parse panel type from DisplayID 2.x Display Parameters UAPI: - KFD interface for applications to select sigbus behavior on fatal errors Proposed userspace: https://github.com/ROCm/rocm-systems/pull/6190 From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260702141515.67919-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-07-07Merge tag 'drm-xe-next-2026-07-03' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - Add additional error components to xe drm_ras (Riana) - Drop 'force_execlist' module parameter (Roper) Cross-subsystem Changes: - Perf events: Export perf_allow_{cpu,tracepoint} to be used by Xe (John) Display Changes: - Skip FORCE_WC and vm_bound check for external dma-bufs (Auld) Driver Changes: - Gate observation streams with perf_allow_cpu (John Hubbard) - Documentation updates and fixes (Michal, Zhan) - Remove unreleased NVL-S GuC (Daniele) - Fix pcode init path (Michal) - RTP fixes and improvements (Gustavo, Violet, Thomas, Roper) - TLB invalidation fixes and improvements (Tilak) - PXP detachment from HuC for newer platforms (Daniele) - Multi-queue fix (Niranjana) - Improve Kconfig.profile help (Rodrigo) - Xe_drm_ras and hw_error updates and fixes (Raag, Riana) - NVL-S updated PCI-IDs and W/a (Gustavo, Nitin) - Fix dma_fence refcound (Wentao) - Madvise: optimize invalidation path (Arvind) - Fix a infinite gt-reset loop in the timeout recovery (Rodrigo) - Fix wa_oob codegen recipe for external module builds (Thomas) - Avoid global forcewake in cycle query path (Xin) - Update TTM device benefical_order (Brost) - Fix buffer overflow in guc capture (Tejas) - Page-table fixes and improvements (Brian, Francois, Auld, Brost) - Removing redundant check (Lu) - General MCR and MMIO clean-up and improvements (Michal) - Don't whitelist OA registers unconditionally (Ashutosh) - SVM error return fix (Brost) - Userptr fix and small related clean-ups (Shuicheng) - Don't attempt to process FAST_REQ or EVENT relays on PF (Michal) - Couple fdinfo improvements (Auld) - Drop manual VF check on i2c (Raag) - Probe info outside of xe_info_init functions (Gustavo) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/akf7xr96MI4Rd6Qj@intel.com
2026-07-03drm/xe: Documentation: fix chars used for subsectionRafael Passos
Fixes "ERROR: A level 2 section cannot be used here". Equal signs are reserved for document titles. This file docs gets imported by driver-uapi.rst, and the page title is defined there. Signed-off-by: Rafael Passos <rafael@rcpassos.me> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Link: https://patch.msgid.link/20260701012141.167868-1-rafael@rcpassos.me Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [Rodrigo modified the subject while pushing it]
2026-06-30Merge drm/drm-next into drm-misc-nextThomas Zimmermann
Backmerging to get drm-misc-next to v7.2-rc1. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
2026-06-29drm/edid: parse panel type from DisplayID 2.x Display ParametersChenyu Chen
Parse the Display Parameters Data Block (tag 0x21) defined in DisplayID v2.1a Section 4.2.6. Extract the Display Device Technology field from the color depth and device technology byte, which indicates whether the panel uses LCD or OLED technology. Add a panel_type field to struct drm_display_info and populate it during DisplayID iteration so downstream drivers can use it for panel-type-dependent behavior. Add DRM_MODE_PANEL_TYPE_LCD to the UAPI panel type property alongside the existing OLED value. Assisted-by: Copilot:Claude-Opus-4.6 Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Link: https://patch.msgid.link/20260526030254.1460480-3-chen-yu.chen@amd.com Signed-off-by: Mario Limonciello <superm1@kernel.org>
2026-06-22drm/xe/uapi: Add additional error components to xe drm_rasRiana Tauro
Add additional Error components supported by XE drm_ras (Reliability, Availability and Serviceability). Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patch.msgid.link/20260618060633.2790109-9-riana.tauro@intel.com Signed-off-by: Riana Tauro <riana.tauro@intel.com>
2026-06-17drm/edid: parse panel type from DisplayID 2.x Display ParametersChenyu Chen
Parse the Display Parameters Data Block (tag 0x21) defined in DisplayID v2.1a Section 4.2.6. Extract the Display Device Technology field from the color depth and device technology byte, which indicates whether the panel uses LCD or OLED technology. Add a panel_type field to struct drm_display_info and populate it during DisplayID iteration so downstream drivers can use it for panel-type-dependent behavior. Add DRM_MODE_PANEL_TYPE_LCD to the UAPI panel type property alongside the existing OLED value. Assisted-by: Copilot:Claude-Opus-4.6 Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-17drm/amdgpu: add ioctl to handle RAS poison errorYifan Zhang
Add a new DRM_IOCTL_AMDGPU_PROC_OPTIONS ioctl with the AMDGPU_PROC_OPTIONS_OP_KFD_SIGBUS_DELAY option, allowing userspace (ROCr) to control per-process SIGBUS delivery. Userspace for this can be found at: https://github.com/ROCm/rocm-systems/pull/6190 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-06-05drm/panthor: Support sparse mappingsAdrián Larumbe
Allow UM to bind sparsely populated memory regions by cyclically mapping virtual ranges over a kernel-allocated dummy BO. This alternative is preferable to the old method of handling sparseness in the UMD, because it relied on the creation of a buffer object to the same end, despite the fact Vulkan sparse resources don't need to be backed by a driver BO. The choice of backing sparsely-bound regions with a Panthor BO was made so as to profit from the existing shrinker reclaim code. That way no special treatment must be given to the dummy sparse BOs when reclaiming memory, as would be the case if we had chosen a raw kernel page implementation. A new dummy BO is allocated per open file context, because even though the Vulkan spec mandates that writes into sparsely bound regions must be discarded, our implementation is still a workaround over the fact Mali CSF GPUs cannot support this behaviour on the hardware level, so writes still make it into the backing BO. If we had a global one, then it could be a venue for information leaks between file contexts, which should never happen in DRM. As a side note, care was put to adjust dummy BO offsets for sparse mappings so that all addresses in the new VA are mapped aligned against it. Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20260522185206.2798288-6-adrian.larumbe@collabora.com Signed-off-by: Steven Price <steven.price@arm.com>