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path: root/drivers/gpu/drm/msm/registers/adreno
AgeCommit message (Expand)Author
2026-10-05drm/msm: Sync registers from mesaRob Clark
2026-09-27drm/msm/a8xx: Add Adreno 850 supportAkhil P Oommen
2026-09-11drm/msm/a6xx: Add CX AO Counter registers used for a750 GPUsNeil Armstrong
2026-07-18drm/msm/a6xx: Rename GBIF_CX_CONFIG to a A6XX- variant registerAkhil P Oommen
2026-07-16drm/msm/a3xx: Drain VBIF before GPU suspendAlexandre MINETTE
2026-05-29drm/msm/registers: Add perfcntr jsonRob Clark
2026-05-29drm/msm/adreno: Sync registers from mesaRob Clark
2026-03-31drm/msm/a6xx: Add soft fuse detection supportAkhil P Oommen
2026-03-31drm/msm/a8xx: Fix the ticks used in submit tracesAkhil P Oommen
2025-11-18drm/msm/adreno: Introduce A8x GPU SupportAkhil P Oommen
2025-11-18drm/msm/a8xx: Add support for A8x GMUAkhil P Oommen
2025-11-18drm/msm/a6xx: Rebase GMU register offsetsAkhil P Oommen
2025-11-18drm/msm/a6xx: Sync latest register definitionsAkhil P Oommen
2025-11-18drm/msm/adreno: Common-ize PIPE definitionsAkhil P Oommen
2025-09-10drm/msm/registers: Sync GPU registers from mesaRob Clark
2025-09-10drm/msm/registers: Make TPL1_BICUBIC_WEIGHTS_TABLE an arrayRob Clark
2025-09-08drm/msm: Update GMU register xmlAkhil P Oommen
2025-08-07drm/msm: Fix a7xx debugbus readRob Clark
2025-07-04drm/msm: Update register xmlRob Clark
2025-06-09drm/msm: Fix CP_RESET_CONTEXT_STATE bitfield namesConnor Abbott
2025-04-18drm/msm/a6xx+: Don't let IB_SIZE overflowRob Clark
2025-01-03drm/msm: registers: Add GMU FW version registerKonrad Dybcio
2024-10-03drm/msm/a6xx: Sync relevant adreno_pm4.xml changesAntonino Maniscalco
2024-10-03drm/msm: Add CONTEXT_SWITCH_CNTL bitfieldsAntonino Maniscalco
2024-08-30drm/msm: Update a6xx register XMLConnor Abbott
2024-05-04drm/msm: Update a6xx registers XMLConnor Abbott
2024-04-22drm/msm: import A6xx XML display registers databaseDmitry Baryshkov
2024-04-22drm/msm: import A5xx XML display registers databaseDmitry Baryshkov
2024-04-22drm/msm: import A2xx-A4xx XML display registers databaseDmitry Baryshkov