linux.git - Linux kernel mainline source

Age	Commit message (Collapse)	Author
2026-09-19	fpga: xilinx-selectmap: control CSI_B and RDWR_B during configuration	Heiko Schocher
	The driver requests the optional CSI_B and RDWR_B GPIOs with GPIOD_OUT_HIGH and never touches them again. That flag carries a logical value, so both signals end up asserted from probe on, whatever polarity the device tree states, and they stay asserted for the lifetime of the device. Neither signal belongs to the driver's lifetime. CSI_B (Chip Select) selects the device on the SelectMAP port, RDWR_B (Read/Write) selects the transfer direction, so both belong to the data transfer. A device that is never deselected never lets go of the port, and a port pinned to write mode cannot be read back. Keep the two descriptors in the driver private data, request them deasserted, and assert them only around the configuration data transfer. RDWR_B is asserted first, UG470 describes in chapter "SelectMAP ABORT" that changing it while the device is selected aborts the configuration on the next CCLK. Signed-off-by: Heiko Schocher <hs@nabladev.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20260909112200.13256-1-hs@nabladev.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
2026-07-03	Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c ↵	Uwe Kleine-König (The Capable Hub)
	files) Replace the #include of <linux/mod_devicetable.h> by the more specific <linux/device-id/*.h> where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich <dakr@kernel.org> Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
2024-03-31	fpga: xilinx-selectmap: add new driver	Charles Perry
	Xilinx 7 series FPGA can be programmed using a parallel port named the SelectMAP interface in the datasheet. This interface is compatible with the i.MX6 EIM bus controller but other types of external memory mapped parallel bus might work. xilinx-selectmap currently only supports the x8 mode where data is loaded at one byte per rising edge of the clock, with the MSb of each byte presented to the D0 pin. Signed-off-by: Charles Perry <charles.perry@savoirfairelinux.com> [yilun.xu@linux.intel.com: replace data type of i from u32 to size_t] Acked-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20240321220447.3260065-4-charles.perry@savoirfairelinux.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>