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4 daysMerge tag 'riscv-for-linus-7.4-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: - Add support for crash hotplug - Improve user copy performance on cores with fast misaligned accesses - Optimize code paths involving pgtable_l{4,5}_enabled() by patching in the return values during early boot (since these don't change during runtime), or by specifying the return values directly in Kconfig files (for purpose-built kernels) - Change the PCIe bus reassignment behavior to depend on the PCI_REASSIGN_ALL_BUS PCI flag (as ARM64 does) - Avoid an unnecessary sstatus CSR read during context switch - Make the sbi_ecall() macro variadic, improving code clarity - Refactor __switch_to_vector() to prepare for upcoming vector context switch optimizations - Add a kselftest for vectorized user copy - Add bounds checking on the shadow stack restore token address to avoid it being used as an attack vector - Fix the shadow stack and indirect branch landing pad control functions to only update the CPU's envcfg CSR when operating on the current task - For MIPS RISC-V systems, add support for early boot-applied errata; and for P8700 RISC-V systems, avoid WFI usage in the kernel (since it is buggy) - Add the "B" RISC-V ISA extension to hwcap and hwprobe reporting - Add support for specifying and reporting the "Zic64b" RISC-V ISA extension, and add it to the SpacemiT K1, K3, and Sophgo SG2044 DT files - Require the block size of cache management operations to be specified in DT schema validation for the RISC-V ISA extensions Zicbom, Zicbop, and Zicboz - Some miscellaneous fixes: fix an incorrect bitfield width in the RVG_SYSTEM_CSR_MASK bitmask macro; make RISCV_ALTERNATIVE mandatory, now that XIP kernel support has been removed; and remove some unnecessary includes in kernel/smp.c * tag 'riscv-for-linus-7.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits) riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57 riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled riscv: convert pgtable_l4|l5_enabled to inline function riscv: remove RISCV_ALTERNATIVE Kconfig option riscv: Add a getter for user PMLEN support riscv: dts: sophgo: sg2044: Add Zic64b ISA extension riscv: dts: spacemit: k1: Add Zic64b ISA extension riscv: dts: spacemit: k3: Add Zic64b ISA extension riscv: Add Zic64b to cpufeature and hwprobe dt-bindings: riscv: Add Zic64b extension description dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz riscv: Add B to hwcap and hwprobe riscv: remove unused profile.h includes riscv: cfi: Only write envcfg CSR when task is current riscv: cfi: Bounds check restore token before swap riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause selftest: riscv: test vectorized user copy riscv: vector: refactor context switch for kernel-mode vector riscv: do not read csr in vector context switch ...
8 daysMerge tag 'kexec-v7.4-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux Pull kexec updates from Mike Rapoport: - Fix probe error codes and error propagation: - make architecture functions that probe loaded image consistenly return -ENOEXEC when they do not recognize the image format - make kexec_image_probe_default() distinguish image format mismatches (-ENOEXEC) from real errors (e.g. -ENOMEM), propagating real errors immediately and only continuing to the next loader on -ENOEXEC - Make sure the next kernel does not land on hardware-poisoned pages - Remove unused arch_kexec_locate_mem_hole hook * tag 'kexec-v7.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux: kexec_file: remove unused arch_kexec_locate_mem_hole hook kexec: fix error propagation in kexec_image_probe_default() kexec: return -ENOEXEC from image probe functions on mismatch kexec: keep the next kernel off hardware-poisoned pages kexec_file: stop the top-down search before it underflows
12 daysMerge tag 'timers-vdso-2026-10-20' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull VDSO updates from Thomas Gleixner: "Updates for the VDSO subsystem: - Ensure that the CLOCK_AUX base calculations are properly scaled against the base timekeeper. The update function failed to take the fractional nanosecond part into account, which results in a rounding error. - Cleanup and consolidate the vsyscall headers to get rid of pointless copies all over the architectures. - Replace a runtime conditional in the time getter function for namespaced clocks by simple pointer arithmetic which speeds up the read function" * tag 'timers-vdso-2026-10-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: vdso/vsyscall: Keep the CLOCK_AUX base scaled vdso/math64: Add and use __iter_div64_u64_rem() vdso/math64: Use OPTIMIZER_HIDE_VAR() in __iter_div_u64_rem() vdso/gettimeofday: Avoid runtime conditional in do_hres_timens() vdso: Remove __ASSEMBLER__ guards from vsyscall.h vdso: Add asm-generic/vdso/vsyscall.h vdso: Remove unnecessary vdso/vsyscall.h includes riscv/hwprobe: Include vdso/datapage.h arm64/vdso: Delete asm/vdso/vsyscall.h inclusions x86/vdso: Delete asm/vdso/vsyscall.h inclusions sparc/vdso: Delete asm/vdso/vsyscall.h inclusion s390/vdso: Delete asm/vdso/vsyscall.h inclusions sparc/vdso: Move __VDSO_PAGES to asm/vdso.h x86/vdso: Move vDSO page definitions to asm/vdso.h vdso: Delete asm-generic/vdso/vsyscall.h vdso/vsyscall: Define fallback time synchronization functions in vsyscall.c vdso/getrandom: Define fallback __arch_get_vdso_u_rng_data() in getrandom.c vdso/gettimeofday: Define fallback __arch_get_vdso_u_time_data() in gettimeofday.c vdso: Move the kernel-side time update helpers to a new header
12 daysMerge tag 'irq-drivers-2026-10-20' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq chip driver updates from Thomas Gleixner: "Updates for interrupt chip drivers: - Remove the futile attempts to cleanup resources when the probing of the main interrupt chip fails for SiFIVE/PLIC devices. If that probe fails the system will stall immediately afterwards in the boot process without reaching a state where the error could be diagnosed. The lack of resource cleanup led to a frenzy of AI detected/assisted "fixes" which just make the code pretend to be correct for no value. Remove the existing half baked cleanup and immediately panic the machine when the probe fails. That's far more useful than letting it proceed and stall out a millisecond later with no information about the root cause. - A series of fixes for the ARM GIC-V3 driver addressing a potential double free, a bitmask overrun on 32-bit ARM and a OF node leak. - Automatically set the IRQ_DOMAIN_FLAG_DESTROY_GC when a interrupt domain is created that also allocates the generic interrupt chip during domain creation. That removes the requirement for manually setting the flag in the domain creation info structure when it contains a valid entry for allocating the generic interrupt chip. Remove the therefore redundant setters of IRQ_DOMAIN_FLAG_DESTROY_GC in the existing drivers. - Add support for Annapurna Labs FIC version 2 and 3 and implement affinity control for the demultiplexed interrupts by utilizing the recently merged interrupt redirection infrastructure. - Convert the ACPI device ID structures to named initializers - Consolidate the IPI related constants for RISC-V interrupt controllers - Add support for Qualcomm Purwa SoC interrupt chip and consolidate the workaround for the previous version in Hamoa SoCs. - The usual small fixes and improvements all over the place" * tag 'irq-drivers-2026-10-20' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (61 commits) irqchip/al-fic: Support per-child affinity via interrupt redirection irqchip/al-fic: Add support for FIC v3 irqchip/al-fic: Support error and fatal outputs and FIC v2 dt-bindings: interrupt-controller: amazon,al-fic: Add mask selection irqchip/al-fic: Switch to shared parent interrupt irqchip/al-fic: Keep the device_node instead of a cached name string irqchip/al-fic: Use %pOF and raise init log level irqchip/al-fic: Use %pe to print init error irqchip/al-fic: Fix coding style issues irqchip: Use named initializers for acpi_device_id irqchip/gic-v5: Fix standalone IRSes OF probe dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints irqchip/renesas-rzv2h: Preserve TIEN state in rzv2h_tint_set_type() irqchip/loongson-eiointc: Use pa_to_nid() rather than hard-code irqchip/riscv-imsic: Expose the fwnode via the global config irqchip/meson-gpio: Allow the GPIO interrupts to wake the system irqchip/gic-v3: Ensure change to DS is visible irqchip/mips-gic: Transfer interrupt mask state across clusters irqchip/mips-gic: Fix recursive acquisition of gic_lock in gic_set_affinity() irqchip/mips-gic: Fix unbalanced cm_core_lock in for_each_online_cpu_gic() ...
12 daysMerge tag 'kbuild-7.4-1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux Pull Kbuild / Kconfig updates from Nathan Chancellor: "Kbuild: - Suppress compiler flags in debug info for external module builds - Use '-fmacro-prefix-map' in more places in the build - Merge initial set of changes from Lorenzo's speed up series, along with some fixes found through testing: - Avoid allocating .modinfo in vmlinux - Speed up kallsyms by indexing symbols by token and outputting binary data to disk directly then including in assembly via .incbin - Don't sort $(NM) output when unnecessary - Only emit relocations on the final vmlinx link - Reimplement mksysmap in C - Move many cc-option and ld-option calls into the Kconfig stage to cache their results - Use pigz for gzip compression when available - Move gen_init_cpio and gen_initramfs.sh from usr/ to scripts/ - Add a TOML configuration to scripts/container and update documentation accordingly - Add a generic, opt-in mechanism for checking that headers can compile standalone - Update machine function splitting argument for LLVM 24 rename in AutoFDO build - Miscellaneous minor clean ups, fixes, and hardening, mostly found/fixed via LLMs Kconfig: - Turn recursive ranges into an error - Fix savedefconfig for defaults that were adjusted for being out of range and revert a previously applied workaround - Improvements and hardening around integer and hexadecimal values - Emit a warning when selecting or implying a choice symbol, which has no effect - Emit a warning when KCONFIG_PROBABILITY is malformed - Introduce def_string / def_int / def_hex to mirror the existing def_bool / def_tristate to succinctly set a value and type at the same time. - Add cc-option-str and ld-option-str macros to act like Kbuild's cc-option and ld-option, returning the string when the option is supported, allowing many checks to be moved into Kconfig - Minor usability improvements to Kconfig tests" * tag 'kbuild-7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux: (59 commits) kbuild: AutoFDO: Update split machine function argument for upstream rename kbuild: Mark the initcall ordering recipe as recursive kbuild: Mark the gzip recipes as recursive localmodconfig: Explicitly report boolean configs during integrity check scripts/make_fit: Ignore schema checks when decomposing DTBs clang-tools: Import os for broken pipe handling kconfig: use the value argument in sym_get_near_range_bound() kconfig: fix infinite loop in conf_choice() when no choice value is visible kconfig: cleanup stale comment about 'keys' array kconfig: Improve ergonomics around disabling warnings with cc-option scripts/Kconfig.toolchain: Drop compiler symbols from dependencies checkkconfigsymbols.py: Parse Git status output line by line gen_init_cpio: stop parsing on lines with a missing argument list .gitignore: drop Module.markers .gitignore: ignore pacman package signatures kbuild: add header check facility as a manually run static analyzer Documentation: dev-tools: refer to user ID rather than id Documentation: dev-tools: update container.rst with config file scripts: add TOML config to container tool kconfig: tests: {old,save}defconfig: Forward dynamic keyword arguments ...
13 daysMerge tag 'perf-core-2026-10-18' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf events updates from Ingo Molnar: - Support SIMD/eGPRs/SSP register sampling in perf (Dapeng Mi, Kan Liang) - Turn amd_uncore_ctx events into a flexible array (Rosen Penev) - Finish the work related to fixing the guest PEBS path to not set unwanted PERF_GLOBAL_CTRL bits, for which urgent fixes are upstream already (Sean Christopherson) - Drop redundant counter slot searches in the AMD uncore driver (Usama Arif) - Don't WARN when the ext_regs_buf allocation fails (vineash) - Annotate x86_pmu::hybrid_pmu with __counted_by_ptr (Thorsten Blum) * tag 'perf-core-2026-10-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (34 commits) perf/x86: Don't WARN when the ext_regs_buf allocation fails perf/x86/amd/uncore: Free counter slot by index perf/x86/amd/uncore: Remove redundant event slot scan perf/x86/intel: Check only PMC bits in PEBS_ENABLED when detecting host PEBS usage KVM: VMX: Only tell perf to enable PEBS counters for fully enabled PMCs KVM: VMX: Drop a redundant pmu->global_ctrl check when processing pebs_enable perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM perf/x86: KVM: Have perf define a dedicated struct for getting guest PEBS data perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask perf/x86/intel: Annotate x86_pmu::hybrid_pmu with __counted_by_ptr perf/x86/amd/uncore: Turn amd_uncore_ctx events into a flexible array perf/x86/intel: Add sanity check for PEBS record/fragment size perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs perf/x86/intel: Advertise PERF_PMU_CAP_SIMD_REGS capability perf/x86/intel: Support arch-PEBS based SIMD/eGPRs sampling perf/x86: Support SSP sampling using sample_regs_* fields perf/x86: Support eGPRs sampling using sample_regs_* fields perf: Enhance perf_reg_validate() with simd_enabled argument perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields perf/x86: Support ZMM sampling using sample_simd_vec_reg_* fields ...
13 daysMerge tag 'sched-core-2026-10-18' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull scheduler updates from Ingo Molnar: "Kconfig updates: - Simplify PREEMPT_DYNAMIC (Mark Rutland) Fair scheduler updates: - Remove redundant RUN_TO_PARITY check (Elif Topuz) - Declare augmented callbacks per field, fix rb_add_augmented_cached() descent (Yiwei Lin, Peter Zijlstra) - Restart fair hrtick after same-task repicks (Shubhang Kaushik) - Improve the scheduling latency of short slice tasks (Vincent Guittot) Deadline/RT scheduler updates: - Check start_dl_timer expiry with ktime_before() (Liang Hao) - irq_work: CPU-hotplug improvements on PREEMPT_RT (Sebastian Andrzej Siewior) Energy-aware scheduling updates: - Implement the steal_governor, introduce preferred CPUs and steal-driven vCPU backoff (Shrikanth Hegde) Multi-processor load-balancing updates: - Enable preferred SMT siblings on NVIDIA Olympus (Andrea Righi) - Randomize equally shallow idle CPU picks (Christian Loehle) - Remove redundant core_sched_seq (Hui Su) Cache-aware scheduling updates: - Avoid publishing partial LLC utilization (Jemmy Wong) NUMA-balancing updates: - Reset NUMA fault locality after scan period update (Eric Kim) Proxy execution updates: - Ongoing work to implement sleeping owner handling for proxy execution (John Stultz, Vasily Gorbik) - Preparatory steps to make sched_ext compatible with proxy execution (Andrea Righi) Scheduler infrastructure updates & fixes: - Remove the RCU wait from PSI trigger destruction (Shakeel Butt) - Avoid modifying wait-entry on failed priority registration (Hui Su) - Use the new static key API for sched_feat (Hongyan Xia) - Convert paravirt_steal to new static key APIs (Hongyan Xia) - cputime: Don't account idle time twice after dyntick-idle (Stian Halseth) Scheduler debugging updates: - Set TIF_NEED_RESCHED before calling __trace_set_need_resched() (Sechang Lim) - Fix context analysis errors in non-preferred CPU push (Shrikanth Hegde) Misc cleanups and fixes by Christian Loehle, Shubhang Kaushik, Thomas Huth and Vladimir Zapolskiy" * tag 'sched-core-2026-10-18' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (64 commits) sched: Replace nr_iowait_cpu() with a bool accessor Revert "sched/fair: Remove dead code on enqueue_task_fair()" sched/cache: Avoid publishing partial LLC utilization sched/cputime: Don't account idle time twice after dyntick-idle sched/psi: Remove the RCU wait from trigger destruction sched/eevdf: Remove redundant RUN_TO_PARITY check sched/wait: Avoid modifying entry on failed priority registration rbtree_test: Use rb_add_augmented_cached() for the cached augmented test rbtree: Update augmented data on the way down in rb_add_augmented_cached() rbtree: Declare augmented callbacks per field with RB_AUG() rbtree_test: Use rb_add() and rb_add_cached() for the basic tests smpboot: Don't park the thread if work is pending irq_work: Flush lazy work CPU down on PREEMPT_RT irq_work: Update a comment regarding CPU hotplug invocation sched/topology: Add asymmetric SMT packing override sched/fair: Honor asymmetric SMT priority in idle selection sched: Set TIF_NEED_RESCHED before calling __trace_set_need_resched() sched/core: Fix context analysis errors in non-preferred CPU push virt/steal_governor: Enable the driver virt/steal_governor: Implement steal_governor policy loop ...
2026-10-15vdso: Remove unnecessary vdso/vsyscall.h includesThomas Weißschuh
None of these files uses anything from the header. Remove the inclusion. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260909-vdso-asm-generic-vsyscall-h-v1-13-63ae856cc659@linutronix.de
2026-10-15riscv/hwprobe: Include vdso/datapage.hThomas Weißschuh
The symbol vdso_k_arch_data is provided by vdso/datapage.h, which is currently not included explicitly. An upcoming refactoring will remove the currently used transitive inclusion. Add an explicit inclusion. Signed-off-by: Thomas Weißschuh <thomas.weissschuh@linutronix.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Link: https://patch.msgid.link/20260909-vdso-asm-generic-vsyscall-h-v1-12-63ae856cc659@linutronix.de
2026-10-15Merge branch 'kexec-7.4' into kexec-nextMike Rapoport (Microsoft)
2026-10-13Merge branch 'tip/sched/urgent'Peter Zijlstra
Pickup dependencies; notably the RB-tree fix. Signed-off-by: Peter Zijlstra <peterz@infradead.org>
2026-10-08riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabledJisheng Zhang
The pgtable_l4|[l5]_enabled check sits at hot code path, performance is impacted a lot. Since pgtable_l4|[l5]_enabled isn't changed after boot, we can use alternative mechanism to optimize them. So the question is whether we can add RISCV_ISA_EXT_SV48/SV57 and use riscv_has_extension_*() or not. Per [1] and [2], SV48 and SV57 are ISA exensions too. From another side, riscv_has_extension_[un]likely() and other related functions report whether the extension is supported and enabled on the platform. So SV48 and SV57 can be supported with current isa extension alternative mechanism. However, to use it to optimize pgtable_l4|l5_enabled, we have to support the "early" characteristic, I.E besides risc_isa bitmap setting, we need to support appling alternative early before MMU on. After that, use it to optimize pgtable_l4|l5_enabled. For the typical access_ok(addr, 1); before the patch: ... auipc a5,0xb43 lbu a5,100(a5) # ffffffff80b51f68 <pgtable_l5_enabled> bnez a5,ffffffff8000ef46 <foo+0x56> auipc a5,0xb43 lbu a5,91(a5) # ffffffff80b51f69 <pgtable_l4_enabled> beqz a5,ffffffff8000ef5a <foo+0x6a> ... after the patch: These memory load and test branch instructions are replaced with only two j or nop instructions. Initial test lmbench's lat_syscall write on TH1520 platforms shows that the write syscall latency is reduced by about 2.38%. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://github.com/riscv/riscv-isa-manual/blob/main/src/profiles/profiles.adoc [1] Link: https://riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+ISA+Extensions [2] Link: https://patch.msgid.link/20261008150045.28905-4-jszhang@kernel.org [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: convert pgtable_l4|l5_enabled to inline functionJisheng Zhang
This is the preparation of optimizing pgtable_l4|l5_enabled(). No functionality change. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Link: https://patch.msgid.link/20261008150045.28905-3-jszhang@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: remove RISCV_ALTERNATIVE Kconfig optionJisheng Zhang
riscv always selects RISCV_ALTERNATIVE now, so we can remove this Kconfig option and enable RISCV_ALTERNATIVE code unconditionally. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20261008150045.28905-2-jszhang@kernel.org [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: Add a getter for user PMLEN supportAndrew Jones
Querying whether a given user PMLEN is supported is needed for RVA23U64 base detection from outside arch/riscv/kernel/process.c. Add riscv_have_user_pmlen() to expose this. Link: https://lore.kernel.org/linux-riscv/rfuwa7a3ebe76udmnwyrssjy7shkkgxntvhwzn6oquysj4tuyp@xzvpylcfhz53/ Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Guodong: replace exported booleans with getter per Andrew's suggestion] Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-8-5f14bc5c23d3@oss.qualcomm.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: Add Zic64b to cpufeature and hwprobeQingwei Hu
Zic64b mandates 64-byte naturally aligned cache blocks and is a mandatory extension of the RVA22 and RVA23 profiles. Allocate a RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a validate callback that requires each cbom/cbop/cboz cache block size to be 64 bytes when it is present, and export it through hwprobe. Link: https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059 Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Qingwei Hu <qingwei.hu@bytedance.com> Co-developed-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-4-5f14bc5c23d3@oss.qualcomm.com [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: Add B to hwcap and hwprobeAndrew Jones
Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs are all set. Also expose B via hwprobe (RISCV_HWPROBE_EXT_B in RISCV_HWPROBE_KEY_IMA_EXT_1) so that userspace can probe B directly, mirroring the F/D/C/V pattern where each is reported via both hwcap and hwprobe. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [guodong.xu: Add B to hwprobe] Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-1-5f14bc5c23d3@oss.qualcomm.com [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: remove unused profile.h includesAnthony Iliopoulos
None of the code in these files uses declarations provided by profile.h. Remove the unnecessary header includes across the various files to clean up dependencies and reduce include bloat. Signed-off-by: Anthony Iliopoulos <ailiop@suse.com> Link: https://patch.msgid.link/20260820131309.14014-1-ailiop@suse.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: cfi: Only write envcfg CSR when task is currentSamuel Holland
set_shstk_status() and set_indir_lp_status() take a task argument, which lets them operate on tasks other than current, but they always write the envcfg CSR for the current task. Fix this with the envcfg_update_bits() helper, which only writes the envcfg CSR when operating on current. Fixes: 61a0200211d31e ("riscv: Implement arch-agnostic shadow stack prctls") Fixes: 8a9e22d2ca5855 ("riscv: Implement indirect branch tracking prctls") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20261007155748.291814-2-samuel.holland@sifive.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: cfi: Bounds check restore token before swapSamuel Holland
Currently the user-provided shadow stack restore token is not checked before being used as the address in ssamoswap.d. While an invalid restore token will be caught and raise SIGSEGV, this happens after writing 4 bytes of zeroes anywhere in the address space. Check that the restore token is at least a valid user address before the swap to ensure we do not scribble over kernel memory. Fixes: 66c9c713de59 ("riscv/signal: save and restore the shadow stack on a signal") Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20261007155748.291814-1-samuel.holland@sifive.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pauseDjordje Todorovic
The MIPS P8700 has bugs with the WFI instruction. A WFI instruction after a mispredicted branch can result in erroneous address translation on the MIPS P8700. MIPS has not published an erratum for this. The workaround uses the RISC-V alternatives framework to patch all WFI instructions with the MIPS P8700 pause opcode (0x00501013) at runtime when running on P8700 hardware. Two call sites are patched: - arch/riscv/kernel/head.S: secondary hart parking loop - arch/riscv/include/asm/processor.h: wait_for_interrupt() Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com> Link: https://patch.msgid.link/20260917-p8700-wfi-v3-1-ada4b0584712@htecgroup.com [pjw@kernel.org: updated to apply] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-07riscv: vector: refactor context switch for kernel-mode vectorAndy Chiu
When context switching out a thread in preemptible kernel-mode vector, there are 2 distinct cases: One is voluntary switch and the other is trap-introduced switch. We don't need to save vector context for voluntary switch and the context is always !dirty as long as we clear the dirty bit at riscv_v_context_nesting_end(). Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Link: https://patch.msgid.link/20260918215154.2481482-3-tchiu@tenstorrent.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-07riscv: do not read csr in vector context switchAndy Chiu
CSR operation can be costly as it may introduces serialization. Instead of reading from sstatus.vs to the detect voluntary context switch in kernel-mode vector, we can read the context depth from riscv_v_flags, as it is always non-zero on a trap-introduced context switch. Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Link: https://patch.msgid.link/20260918215154.2481482-2-tchiu@tenstorrent.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-07riscv: entry: gate shadow call stack reload on sstatus.SPP, not tpZiyi Guo
Under CONFIG_SHADOW_CALL_STACK, handle_exception() reloads the kernel shadow call stack pointer (gp) only when the trap came from userspace. It made that decision with scs_load_current_if_task_changed, which compares the trap-time tp (read back from sscratch into s5) against the current tp: beq \prev, tp, _skip_scs scs_load_current _skip_scs: tp is a user-writable register. A user task that sets tp to the linear-map address of its own task_struct (&current) before trapping makes the comparison succeed (can achieve by brute force with KASLR enable under our test), so the kernel skips scs_load_current and keeps running with the gp that userspace left in place. Under CONFIG_SHADOW_CALL_STACK gp is the shadow call stack pointer and load_global_pointer is a no-op, so the compiler-emitted "sd ra, -8(gp)" / "ld ra, -8(gp)" in every non-leaf function then write to, and return through, an attacker-controlled address -- an unprivileged kernel arbitrary-write and control-flow-hijack primitive. The poisoned gp is saved to task_struct.scs_sp on return, so the reload is skipped on every subsequent entry as well. Decide "came from userspace" from the hardware sstatus.SPP bit (already in s1 at this point) instead of from tp, mirroring the check that ret_from_exception already uses a few instructions later. SPP is written by hardware on trap entry and cannot be forged from U-mode. Legitimate behaviour is unchanged: user entries (SPP=0) reload the task shadow call stack, nested kernel entries (SPP=1) skip it. Fixes: d1584d791a29 ("riscv: Implement Shadow Call Stack") Signed-off-by: Ziyi Guo <guoziyi114@gmail.com> Reviewed-by: Sami Tolvanen <samitolvanen@google.com> Link: https://patch.msgid.link/20261001135711.934152-1-guoziyi114@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-07riscv: ptrace: Zero-initialize regset buffers before copyinZongmin Zhou
user_regset_copyin() only copies `count` bytes, so a PTRACE_SETREGSET request with a short iov_len leaves the rest of the stack buffer uninitialized. In riscv_vr_set() that garbage is validated and copied into the target's vstate, and in riscv_cfi_set() it can be stored as the target's shadow stack pointer. Zero both buffers, as the get path already does. Fixes: 9300f0043974 ("RISC-V: Add ptrace support for vectors") Fixes: 2af7c9cf021c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Signed-off-by: Zongmin Zhou <zhouzongmin@kylinos.cn> Link: https://patch.msgid.link/20260826115711.86861-1-min_halo@163.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-07riscv: ptrace: reject CFI regset access when extensions are absentChen Pei
riscv_cfi_get() and riscv_cfi_set() do not check whether the Zicfilp or Zicfiss extensions are present. On systems without them, PTRACE_GETREGSET on REGSET_CFI still succeeds and returns a zeroed user_cfi_state, misleading debuggers into believing the register set is available, and PTRACE_SETREGSET silently accepts writes that have no effect (e.g. clearing SR_ELP). Reject the access with -EINVAL when neither branch landing pads nor shadow stack is available to userspace, using the same availability helpers as the prctl path. Fixes: 2af7c9cf021c ("riscv/ptrace: expose riscv CFI status and state via ptrace and in core files") Signed-off-by: Chen Pei <cp0613@linux.alibaba.com> Link: https://patch.msgid.link/20260820063233.2567-1-cp0613@linux.alibaba.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-05RISC-V: make use of variadic sbi_ecallRadim Krčmář
The new sbi_ecall doesn't have to list all 8 arguments anymore, so only pass the actual numbers of arguments for each SBI function. The remaining trailing 0 are intentional as they represent an argument. SBI 0.1 shouldn't be using the sbi_ecall, because it's only for 0.2+, but allow it by passing 0 is the reserved register. Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://patch.msgid.link/20250619190315.2603194-3-rkrcmar@ventanamicro.com [pjw@kernel.org: updated to apply; fixed rv64 DBCN WRITE/READ per Radim] Cc: Radim Krčmář <rkrcmar@qti.qualcomm.com> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-05RISC-V: sbi: turn sbi_ecall into variadic macroRadim Krčmář
The SBI ecall interface has 0~6 arguments in a0~a5, and undefined arguments are not reserved, so we don't have to zero the registers. The current sbi_ecall forces programmers to pad the argument count, which makes it hard to distinguish what is a value 0, and what is the padding, because 0 was traditionally used for padding as well. Turn sbi_ecall into a variadic macro that accepts 2~8 arguments, and where only the specified arguments get passed to the ecall instruction. The register a1 is zeroed if unused, to prevent unnecessary leaks of kernel register state from the tracepoints. Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://patch.msgid.link/20250619190315.2603194-2-rkrcmar@ventanamicro.com Cc: Radim Krčmář <rkrcmar@qti.qualcomm.com> Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-05riscv: crash: Add crash hotplug supportRui Qi
When CPUs or memory are hot-plugged on a running system, the crash dump's elfcorehdr -- which describes the available CPUs and memory to the capture kernel -- must be kept in sync, otherwise a crash after a hotplug event would produce a vmcore that does not reflect the current system topology. Enable crash hotplug for RISC-V by selecting ARCH_SUPPORTS_CRASH_HOTPLUG and providing the three architecture hooks invoked through the override macros in <asm/kexec.h>: arch_crash_hotplug_support() reports whether an image supports the mechanism; arch_crash_get_elfcorehdr_size() sizes the segment for NR_CPUS and, with memory hotplug, CRASH_MAX_MEMORY_RANGES; arch_crash_handle_hotplug_event() rebuilds the elfcorehdr through the crash_prepare_headers() helper and writes it over the old segment. The elfcorehdr is copied with memcpy_flushcache(), matching the x86 implementation; on RISC-V this currently expands to a plain memcpy() and will benefit automatically once the architecture provides a flushcache backend. The implementation otherwise follows the x86 crash hotplug model. Signed-off-by: Rui Qi <qirui.001@bytedance.com> Tested-by: Rui Qi <qirui.001@bytedance.com> Link: https://patch.msgid.link/20260910032619.2477279-1-qirui.001@bytedance.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-05riscv: patch: fix handling of bpf-jit execmem addressesWei-Jie Hung
Commit 8718e5a3090b ("riscv: patch: skip fixmap mapping when kernel text is already writable") gated the core_kernel_text() branch of patch_map() on CONFIG_STRICT_KERNEL_RWX, and explicitly left the vmalloc branch unchanged. That branch has a separate problem. That branch only creates a temporary writable fixmap alias when CONFIG_STRICT_MODULE_RWX is enabled, and otherwise assumes the target is directly writable and returns the address unchanged. That assumption no longer holds: bpf_prog_pack_alloc calls set_memory_rox() on every pack unconditionally in alloc_new_pack(), independently of any CONFIG_STRICT_*_RWX option, so BPF text in the vmalloc area is read-only regardless of what CONFIG_STRICT_MODULE_RWX says. With CONFIG_STRICT_MODULE_RWX=n, patch_map() returns the read-only address directly, the subsequent copy_to_kernel_nofault() takes a page fault and returns -EFAULT. bpf_arch_text_copy() turns that into -EINVAL, which propagates through bpf_jit_binary_pack_finalize() to the WARN_ON() in bpf_int_jit_compile() and leaves the program un-JITed. Note that BPF cannot be fixed the way kprobes was in commit bdc46e507b59 ("riscv: mm: make EXECMEM_KPROBES writable without CONFIG_STRICT_MODULE_RWX"). EXECMEM_BPF is already PAGE_KERNEL, i.e. writable at allocation time; the read-only mapping is established afterwards by generic code in alloc_new_pack(), which arch code cannot influence. The only place this can be handled is patch_map(). This is the same problem that was fixed on arm64 by commit b1480ed230ac ("arm64: patching: fix handling of execmem addresses"), and the fix is the same: CONFIG_EXECMEM is what actually tracks whether the vmalloc area can hold executable memory that needs a temporary alias to be written. CONFIG_BPF_JIT, CONFIG_KPROBES and CONFIG_MODULES all select it. Note that this is not limited to CONFIG_MODULES=n. Unlike arm64, riscv selects CONFIG_ARCH_OPTIONAL_KERNEL_RWX, so CONFIG_STRICT_MODULE_RWX can be disabled with CONFIG_MODULES=y as well, and the bug is reachable in that configuration too. The !CONFIG_MMU build is unaffected: it has its own __patch_insn_set() and __patch_insn_write() implementations and never calls patch_map(). Fixes: 2c9e5d4a0082 ("bpf: remove CONFIG_BPF_JIT dependency on CONFIG_MODULES of") Signed-off-by: Wei-Jie Hung <imbigking12@gmail.com> Reviewed-by: Pu Lehui <pulehui@huawei.com> Tested-by: Pu Lehui <pulehui@huawei.com> Link: https://patch.msgid.link/20260914115607.350097-1-imbigking12@gmail.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-05RISC-V: Clear HSTATUS.HU on CPU initializationYong-Xuan Wang
The RISC-V privileged specification does not mandate HSTATUS reset values, leaving the HU bit potentially set after hardware reset. When HU=1, hypervisor instructions (HLV/HLVX/HSV) can execute in U-mode to access guest memory, which may cause unintended behavior if not explicitly controlled. Clear HSTATUS.HU during CPU initialization to ensure hypervisor instructions are only available in HS-mode, preventing unexpected guest memory access from U-mode code. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20260924-hstatus_hu-v2-1-7e970f5f1d8d@sifive.com Cc: stable@vger.kernel.org [pjw@kernel.org: capitalized RISCV_ISA_EXT_h to fix build; added stable cc] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-02Merge tag 'random-7.3-rc6-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/crng/random Pull random number generator fixes from Jason Donenfeld: - VMGENID memory needs to be mapped with the decrypted tag, so that SEV-SNP machines can boot - A fix for an initialization race in VMGENID, followed by a cleanup - Trivial kernel doc cleanups in siphash and random.c - A fix for a new compilation failure with recent clang on PPC and RISC-V, due to generating an out-of-line memset in the vDSO * tag 'random-7.3-rc6-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/crng/random: random: vDSO: avoid call to memset() when zeroing reserved parameter random: fix vgetrandom_opaque_params kernel-doc random: vDSO: fix repeated word 'to' in comment siphash: clean up kernel-doc comments virt: vmgenid: move to using dev_set/get_drvdata virt: vmgenid: set driver_data before registering notification handlers virt: vmgenid: remap memory as decrypted
2026-10-02random: vDSO: avoid call to memset() when zeroing reserved parameterNathan Chancellor
After a recent change in LLVM [1], builds with the random vDSO implementation, such as PowerPC and RISC-V, fail when checking the vDSO: arch/powerpc/kernel/vdso/vdso32.so.dbg: dynamic relocations are not supported arch/riscv/kernel/vdso/vdso.so.dbg: dynamic relocations are not supported memset() is now generated when zeroing params->reserved for some builds because LLVM has an optimization (now run in more instances) that can recognize at compile time when it is assigning a static value to a contiguous area of memory and turn that into a call to memset(). Both clang and GCC assume memset() is always available [2]. Clang has an internal fiddly hook, -max-store-memset, which we can set to a high number, to disable generating out of line memset calls [3]. Similarly, GCC has -finline-stringops=memset to do the same [4], should this issue ever hit future version of GCC. While these options wouldn't make sense for normal kernel code, it is fine for the extremely limited and intentionally compact vDSO code. Link: https://github.com/llvm/llvm-project/commit/90cebef1411617fc3eedd359bdf00cb44b1c2439 [1] Link: https://gcc.gnu.org/onlinedocs/gcc-16.2.0/gcc/Standards.html#index-ffreestanding [2] Link: https://github.com/llvm/llvm-project/commit/b28eeb28bea39148738dc375e8a97072a1907e64 [3] Link: https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#index-finline-stringops [4] Closes: https://github.com/ClangBuiltLinux/linux/issues/2183 Cc: stable@vger.kernel.org # v6.12+ Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
2026-09-26kbuild: avoid re-running compiler and linker probesLorenzo Stoakes (ARM)
Each kernel make invocation begins with ~30 compiler and linker runs each of which performs duplicate probe for a number of compiler and linker options. This is useless work - the compiler and its version is known, so use these to determine which options are available, once. Using the newly introduced cc-option-str, track the result of each probe in CC_OPT_*, LD_OPT_* variables and have Makefile's simply append the symbol. Some care has to be taken around negative options, i.e. -Wno-xxx, as gcc accepts an unknown -Wno- without complaint and only complains later, so instead probe the positive form for these cases. Use CC_HAS_* For those probes that gate a Makefile conditional rather than a simple option, as per the established pattern for this. This change avoids a subtle issue with ppc32 (big endian) - clang doesn't accept -fno-stack-clash-protection on this sub-target, so keep this option in the Makefile. With gcc and clang, defconfig and allmodconfig, the recorded command lines are unchanged, a build with nothing to do rebuilds nothing and W=1 continues to function correctly. Doing this improves all builds, but has a particularly positive impact on no-op builds (builds where nothing has changed). Whole build, 128-thread Threadripper 9980X, best of N runs: before after delta ------------------------------- x86 defconfig, no-op make, gcc 0.78s 0.60s -0.18s (-23%) x86 defconfig, no-op make, clang 0.94s 0.66s -0.28s (-30%) x86 defconfig, touch mm/vma.c, gcc 8.6s 8.5s -0.16s (-2%) x86 defconfig, touch mm/vma.c, clang 8.0s 7.7s -0.24s (-3%) x86 defconfig, clean, clang 29.8s 29.4s -0.37s (-1%) x86 allmodconfig, no-op make, gcc 12.9s 12.7s -0.23s (-2%) x86 allmodconfig, no-op make, clang 14.2s 13.9s -0.29s (-2%) x86 allmodconfig, touch mm/vma.c, clang 32.2s 31.9s -0.30s (-1%) Assisted-by: LLM Signed-off-by: Lorenzo Stoakes (ARM) <ljs@kernel.org> Link: https://patch.msgid.link/20260923-build-speedup-v4-12-73128809a4a4@kernel.org Signed-off-by: Nathan Chancellor <nathan@kernel.org>
2026-09-23Merge branch 'perf/urgent' into perf/core, to resolve conflictIngo Molnar
Conflicts: include/linux/perf_event.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2026-09-10kexec_file: remove unused arch_kexec_locate_mem_hole hookSourabh Jain
No architecture provides an implementation of arch_kexec_locate_mem_hole(). Use kexec_locate_mem_hole() directly and remove the unused fallback wrapper from the kexec header. This simplifies the kexec memory allocation path without changing its behavior. No functional changes intended. The arch hook was introduced by commit f891f19736bd ("kexec_file: Allow archs to handle special regions while locating memory hole"), and its last user was removed by commit 6e5250eaa665 ("powerpc/crash: use generic APIs to locate memory hole for kdump"). Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Mike Rapoport <rppt@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Pasha Tatashin <pasha.tatashin@soleen.com> Cc: Paul Walmsley <pjw@kernel.org> Cc: Pratyush Yadav <pratyush@kernel.org> Cc: linux-riscv@lists.infradead.org Cc: kexec@lists.infradead.org Acked-by: Baoquan He <baoquan.he@linux.dev> Reviewed-by: Mukesh Pilaniya <mpilaniy@redhat.com> Signed-off-by: Sourabh Jain <sourabhjain@linux.ibm.com> Link: https://patch.msgid.link/20260905145835.501635-1-sourabhjain@linux.ibm.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-09-04riscv: sbi: Use IPI_MAX for SBI IPI muxingGUO Ren (XuanTie)
Now that IPI_MAX is visible from <asm/smp.h>, replace the hard-coded BITS_PER_BYTE with the proper symbolic constant in the SBI IPI extension driver. No functional change; IPI_MAX is still 8. Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://patch.msgid.link/20260816070049.2097442-3-guoren@kernel.org
2026-09-04riscv: smp: Move enum ipi_message_type to asm/smp.hGUO Ren (XuanTie)
The IPI message type enumeration (and therefore IPI_MAX) is currently private to arch/riscv/kernel/smp.c. Several IPI providers need to know the exact number of IPIs that the architecture requires, so move the enum into the public header. This is a pure code movement with no functional change. Signed-off-by: GUO Ren (XuanTie) <guoren@kernel.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Radu Rendec <radu@rendec.net> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://patch.msgid.link/20260816070049.2097442-2-guoren@kernel.org
2026-09-02perf: Enhance perf_reg_validate() with simd_enabled argumentDapeng Mi
The upcoming patch will support x86 APX eGPRs sampling by using the reclaimed XMM register space to represent eGPRs in sample_regs_* fields. To differentiate between XMM and eGPRs in sample_regs_* fields, an additional argument, simd_enabled, is introduced to the perf_reg_validate() helper. If simd_enabled is set to 1, it indicates that eGPRs are represented in sample_regs_* fields for the x86 platform; otherwise, XMM registers are represented. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260824082731.1013973-18-dapeng1.mi@linux.intel.com
2026-09-02perf: Eliminate duplicate arch-specific function definitionsDapeng Mi
Define default common __weak functions for perf_reg_value(), perf_reg_validate(), perf_reg_abi() and perf_get_regs_user(). This helps to eliminate the duplicated arch-specific definitions. No function changes intended. Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://patch.msgid.link/20260824082731.1013973-5-dapeng1.mi@linux.intel.com
2026-09-02sched: Convert paravirt_steal to new static key APIsHongyan Xia
paravirt_steal_rq_enabled and paravirt_steal_enabled use raw static_key APIs which are now deprecated. Use the new API instead. No functional change. Signed-off-by: Hongyan Xia <hongyan.xia@transsion.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Juergen Gross <jgross@suse.com> Link: https://patch.msgid.link/20260819081207.12150-1-hongyan.xia@transsion.com
2026-09-02Merge patch series "kexec: fix probe error codes and error propagation"Mike Rapoport (Microsoft)
Mukesh Pilaniya <mpilaniy@redhat.com> says: kexec: fix probe error codes and error propagation While debugging a misleading error on s390x where kexec -s reported "syscall kexec_file_load not available" instead of the actual EINVAL from a kernel command line that exceeded the architecture limit, it was found that some kexec image probe functions return -EINVAL instead of -ENOEXEC for format mismatches, and kexec_image_probe_default() has a bug where it returns whatever the last loader returned rather than always returning -ENOEXEC when no loader matches. * Fix all probe functions to return -ENOEXEC when they do not recognize the image format. * Fix kexec_image_probe_default() to distinguish format mismatches (-ENOEXEC) from real errors (e.g. -ENOMEM), propagating real errors immediately and only continuing to the next loader on -ENOEXEC. kexec-tools patch: https://lore.kernel.org/all/20260814075329.30203-1-mpilaniy@redhat.com/ Link: https://patch.msgid.link/20260821-mpilaniy-v3-0-76b355399d2e@redhat.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-09-02kexec: return -ENOEXEC from image probe functions on mismatchMukesh Pilaniya
Several kexec_file_load() image probe functions return -EINVAL when they do not recognize the image format. A probe function that rejects an image should return -ENOEXEC to indicate that the image is not a recognized executable format. -EINVAL implies a problem with the syscall parameters, not with image recognition. kexec_image_probe_default() iterates through registered loaders and returns the last probe's error code to the caller. That error propagates as the kexec_file_load() return value to userspace. Returning -EINVAL from a probe when no loader matches is semantically incorrect and misleads userspace about the nature of the failure. Return -ENOEXEC from all probe functions and their helpers when the image format is not recognized. Signed-off-by: Mukesh Pilaniya <mpilaniy@redhat.com> Reviewed-by: Philipp Rudo <prudo@redhat.com> Reviewed-by: Pratyush Yadav <pratyush@kernel.org> Reviewed-by: Bradley Morgan <include@grrlz.net> Link: https://patch.msgid.link/20260821-mpilaniy-v3-1-76b355399d2e@redhat.com Signed-off-by: Mike Rapoport (Microsoft) <rppt@kernel.org>
2026-09-01riscv: report Zfhmin/Zvfhmin when Zfh/Zvfh are presentJinRui
The RISC-V ISA manual specifies that Zfh implies Zfhmin, a normative rule clarified in https://github.com/riscv/riscv-isa-manual/pull/3070. Zvfh likewise implies Zvfhmin, as stated by the vector extension specification. The kernel currently reports ZFH and ZFHMIN (and ZVFH and ZVFHMIN) as independent hwprobe bits derived only from what the device tree declares. Platforms that declare just "zfh" (Zfh being a superset that already contains all Zfhmin instructions) therefore report RISCV_HWPROBE_EXT_ZFHMIN=0, which breaks userspace RVA23 conformance checks (e.g. snapd installing core26 on riscv64). Use the existing superset mechanism to set the implied subset bits: - zfh implies zfhmin - zvfh implies zvfhmin Add a hwprobe selftest asserting the implication holds and update the hwprobe documentation accordingly. This is complementary to the rva23u64 base behavior discussion: the RVA23 conformance query proposed there is derived from the per-extension bits fixed here, so correct EXT_0 reporting is a prerequisite for it to work on harts whose device tree declares only "zfh". Tested on a RISC-V QEMU VM whose device tree only declares "zfh" and "zvfh": with this change both /proc/cpuinfo and the hwprobe RISCV_HWPROBE_KEY_IMA_EXT_0 bitmap report ZFHMIN and ZVFHMIN, and the hwprobe selftest (including the new implication check) passes. Link: https://lore.kernel.org/kvm-riscv/20260206002349.96740-1-andrew.jones@oss.qualcomm.com/ Signed-off-by: JinRui <jinrui@haiwei.tech> Link: https://patch.msgid.link/7190E4DB338251C3+20260811081513.2849980-1-jinrui@haiwei.tech [pjw@kernel.org: trimmed superfluous blank line in tags] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-31riscv: hwprobe: initialize pair->value in hwprobe_one_pair()Andy Chiu
The vendor-extension handlers reached from hwprobe_one_pair() (hwprobe_isa_vendor_ext_thead_0() and friends) only OR the present bits into pair->value via VENDOR_EXTENSION_SUPPORTED() and clear their own missing bits; they assume the caller has already zeroed pair->value. That holds for hwprobe_get_values() (it zeroes each pair) and hwprobe_get_cpus() (it re-initializes its scratch pair per key), but not for complete_hwprobe_vdso_data(), which reuses a single pair across all keys without re-zeroing. A vendor key therefore inherits stale bits from the previously probed key, and the wrong value is cached in the vDSO all_cpu_hwprobe_values[] and handed to userspace on the fast patih. Zero pair->value once at the top of hwprobe_one_pair() so every handler starts from a clean value regardless of the caller, and drop the now redundant zeroing in the *_BLOCK_SIZE cases. hwprobe_isa_ext0() keeps its own zeroing because hwprobe_ext0_has() calls it directly, bypassing hwprobe_one_pair(). Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing") Signed-off-by: Andy Chiu <tchiu@tenstorrent.com> Reviewed-by: Jesse Taube <jtaubepe@redhat.com> Link: https://patch.msgid.link/20260725001614.2578617-2-tchiu@tenstorrent.com Cc: stable@vger.kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-31riscv: use string helper in setup_global_riscv_enable()Dmitry Antipov
Prefer the convenient string choice 'str_disabled_enabled()' helper over hardcoded strings in 'setup_global_riscv_enable()'. Signed-off-by: Dmitry Antipov <dmantipov@yandex.ru> Link: https://patch.msgid.link/20260819160546.3219942-1-dmantipov@yandex.ru Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-31Revert "riscv: Reset pmm when PR_TAGGED_ADDR_ENABLE is not set"Samuel Holland
This reverts commit 3033b2b1e3949274f33a140e2a97571b5a307298. The reverted patch is userspace-visible behavior change, not a bug fix. The two variables here (pmm and pmlen) control two independent features: pmm is the _hardware_ pointer masking mode that applies while executing in userspace. pmlen is the shift amount that the _kernel_ uses when untagging addresses; PMLEN_0 means no untagging occurs, so the kernel does not accept tagged addresses in syscall arguments. It is valid (as documented and tested by the self test) to enable pointer masking without enabling the tagged address ABI. This separation is necessary to allow userspace to create an execution environment similar to what the kernel supports on arm64 by default, where TBI is enabled but the tagged address ABI is not. (On arm64, there is no equivalent to PR_PMLEN_MASK because TBI is always enabled.) Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Link: https://patch.msgid.link/20260820014551.1979772-1-samuel.holland@sifive.com Cc: stable@vger.kernel.org Fixes: 3033b2b1e394 ("riscv: Reset pmm when PR_TAGGED_ADDR_ENABLE is not set") Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-31riscv: patch: skip fixmap mapping when kernel text is already writableXiaofeng Yuan
patch_map() always creates a temporary writable mapping via fixmap for kernel text addresses, even when CONFIG_STRICT_KERNEL_RWX is disabled and the kernel text is already mapped with _PAGE_WRITE. This is unnecessary overhead at best, and on minimal configurations it can cause page faults. Skip the fixmap path for kernel text when CONFIG_STRICT_KERNEL_RWX is not enabled, since the text pages are already writable in that case. The module text path is already gated on CONFIG_STRICT_MODULE_RWX and is kept unchanged. Reported-by: Klara Modin <klara@kasm.eu> Closes: https://lore.kernel.org/all/ant_8TaBbov_GS4i@soda.int.kasm.eu/ Reported-by: Lad Prabhakar <prabhakar.csengg@gmail.com> Closes: https://lore.kernel.org/all/CA+V-a8tQK8rih9SGGTyqrEBGpNkx4H0eX2YccCRrgkVAPr+EBg@mail.gmail.com/ Tested-by: Klara Modin <klarasmodin@gmail.com> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://patch.msgid.link/20260814082742.148403-3-xiaofengmian@163.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-25Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds
Pull kvm updates from Paolo Bonzini: "ARM64: - Add support for 'slot' based PMU events, paired with new UAPI that compels the user to select a specific PMU implementation - Lazy save/restore of vCPU state for pKVM, along with various fixes and cleanups to the management of vCPU state between the untrusted host and pKVM hypervisor - Disable traps of EL1 registers for nested hypervisors when FEAT_NV2p1 is present, guaranteeing that EL2-specific register bits are stateful in the EL1 counterpart - Leverage FEAT_NV3 to avoid unnecessary ERET/TLBI traps when the scope of those instructions remains 'in host' (i.e. L1 kernel/userspace) - Pile of fixes for the management of the VNCR pseudo-TLB, such as under-invalidations and races with concurrent TLBIs on other vCPUs - Consolidate the non-protected and pKVM view of ICH_VTR_EL2 to a runtime-patched constant, allowing the same data to be shared with pKVM prior to dropping host privileges - Considerable pile of LLM-assisted fixes around the shop but mostly in the VGIC, our in-kernel generator of bugs (and sometimes interrupts) LoongArch: - Advertise already-supported capabilities - Some bug fixes about timer and MMIO - Some hardening about interrupt injection - Replace kvm_err() with kvm_pr_unimpl() - Add FPU/LSX/LASX test cases for selftests RISC-V: - Svadu/Zicfiss/Zicfilp FWFT support for Guest - Use try_cmpxchg for IMSIC MRIF RMW - More arch-specific tracepoints in KVM RISC-V - Eager page splitting when enabling dirty logging - Optimize hfence request handling for SMP Guests - Improve dirty log clearing by skipping zero bits in mask - Guard HFENCE range loops against overflow - CPU PM notifiers in KVM RISC-V for non-retentive idle states - Fix kernel-mode vector context save/restore for Guest s390: - Fixes for vfio-ap - Fixes for the gmap rework - Fixes for vsie - AI triggered fixes all over - diag9c tracing - code move preparation for the additional arm64 support - enable CONTEXT_ANALYSIS x86: - Perform spring cleaning on x86.{c,h} and asm/kvm_host.h, by adding regs.c (the kvm_cache_regs.h => regs.h is already applied) and msrs.{c,h}, and moving relevant code out of x86.c - Split kvm_mmu in three parts, respectively to describe the format of page tables, walking the guest page tables and building the page tables. Always use the same page table walker kvm->arch.gva_walk as the entry point to convert a guest's virtual address, where the previous code used two different kvm_mmu structs depending on whether the walk included nested EPT/NPT or not. Make page fault vmexits reuse the permission checking machinery that is used for guest page faults. This is both a cleanup and a baby step towards supporting XS/XU memory permissions - Document some of the "fun" gotchas with the APIC base when creating IRQCHIPs on x86 - Remove a defunct masterclock update from kvm_xen_shared_info_init(). It could result in incorrect kvmclock due to triggering an unnecessary switch to/from masterclock mode - Skip Xen runstate time updates if time has effectively gone backwards, so that the guest doesn't report 100% steal time for a very, very long time - Drop KVM's runtime updates of the Xen PV timing CPUID leaf, as KVM was updating the wrong sub-leaf, and upstream KVM will soon provide all the information needed by userspace to populate the CPUID field itself - Fix a bug where KVM would walk a newly created rmap without holding the rmap lock (or mmu_lock) during aging - Fix a bug where aging TDP MMU SPTEs could clobber FROZEN SPTEs - Fix a variety of #DB priority bugs - Fix a class of races related to enabling Hyper-V emulation on a vCPU after the vCPU is visible to the rest of KVM - Use static calls for nested virtualization ops - Move more KVM-internal code out of x86's kvm_host.h - Enumerate support for a variety of Zhaoxin instructions that don't require explicit virtualization - Fix missing EFER validation bugs, including in the KVM_SET_SREGS* path - Harden kvm_vcpu_map() against double-mapping and thus leaking references - Misc fixes and cleanups, e.g. for largely benign syzkaller splats x86 (Intel): - Zero a vCPU's entry in VMX's Posted Interrupt Descriptor table used for IPI virtualization when the vCPU is freed, to fix a use-after-free where hardware will write to a freed vCPU's PID - Service local TLB flushes on a failed nested VM-Enter to fix a bug where KVM could miss a TLB on a future, successful VM-Enter with the same L2 VPID - Cap the maximum value shoved into the VMX Preemption Timer to workaround an erratum that affects all existing Intel CPUs that support CPUID 0x15 - Fix VPID virtualization bugs where KVM would fail to flush hardware TLBs - Harden the TDX "populate" ioctls against bad input, and to prepare for supporting in-place private<=>shared conversion x86 (AMD): - Forcefully invalidate SNP VMSA pages if their backing guest_memfd page is zapped/invalidated, e.g. due to a PUNCH_HOLE in response to a Page-State Change request - Remove a dying VM from the GA Log notifier list before the VM is actually destroyed, to fix a potential use-after-free - While FOLL_WRITE was needed in the past to trigger CoW unsharing, nowadays FOLL_LONGTERM does that already even without FOLL_WRITE, and in fact, get_user_pages() actually disallows FOLL_WRITE together with FOLL_LONGTERM. So don't pass FOLL_WRITE when registering encrypted memory regions, i.e. when pinning SEV/SEV-ES guest memory, to fix a regression with file-backed memory introduced by KVM's (correct) usage of long-term pins (This was reviewed by mm maintainers; for more information, see commit ee1a586dd1fa "KVM: SEV: Drop FOLL_WRITE for encrypted region registration") - Allocate full pages for SEV/SEV-ES {DE,EN}CRYPT ops on SNP-enabled hosts to fix a data corruption issue due to the PSP driver assigning to-be-written pages to firmware (as required by the SNP specs) - Unconditionally intercept ICBEP so that KVM generates the correct guest RIP when handling an ICEBP-induced TASK_SWITCH #VMEXIT - Harden the SNP "populate" ioctls against bad input, and to prepare for supporting in-place private<=>shared conversion Generic: - Remove kvm_debugfs_dir if kvm_init() fails after creating KVM's debugfs - Add a per-VM bitmap to track which vCPU IDs have been "claimed" but for which the vCPU isn't yet online, and use the bitmap to reject duplicate IDs before calling into arch code. This allows arch code to consume vcpu_id without having to worry about cross-vCPU clobbering (at least s390 and x86 have had related bugs) - Rework the so called "prepare" and "invalidate" guest_memfd hooks to prepare for in-place private<=>shared conversion, and clean up a few warts along the way Selftests: - Automatically allocate a full page for L2 guest stacks on x86 instead of requiring test-specific L1 guest code to carve out a portion of the L1 stack for L2 usage, and to ensure the L2 stack also adheres to the x86-64 calling convention ABI - Add a selftest to verify {Guest,Host}-Only behavior in x86's mediated PMU - Clean up nested SVM's handling of GPRs on L2<=>L1 transitions, reuse the functionality for nested VMX, and drop the ucall hack that was fudging around the lack of GPR switching on nVMX - Add a stress test to verify KVM doesn't clobber/drop #PF state, e.g. CR2, across save/restore, including when L2 is active - Add a test to verify KVM_CREATE_VM accepts exactly what is reported by KVM_CAP_VM_TYPES - Misc selftests fixes and cleanups - Fix several issues with seeding the pRNG, and rework the pRNG APIs to that the pRNG can be sanely used in host code, not just guest code - Add an IRQ test to validate virtual IRQ deliverty for IRQs wired up via KVM_IRQFD + KVM_SET_GSI_ROUTING, with optional support for triggering IRQs via writes to an assigned VFIO device - Add syscall wrappers to assert success on a variety of pthreads and CPU affinity APIs - Set vCPU pthread affinity as early as possible to reduce contention issues that were surfaced by PREEMPT_LAZY, which result in runtimes of over a minute on large hosts, versus the expected ~5 seconds - Rework the PMU counters test to run each testcase using a single VM with many vCPUs for each sub-testcase, instead of using a unique VM for each sub-testcase. This cuts the runtime by ~20x Miscellaneous: - MAINTAINERS updates for vfio-ap, guest_memfd, kvm-x86. Mostly representing the status quo more accurately, but also... welcome David Hildenbrand as guest_memfd reviewer!" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (413 commits) KVM: arm64: Validate GICv5 timer PPIs before claiming ownership KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs KVM: arm64: vgic: Prevent speculative SPI array underflow KVM: arm64: vgic: Free gic_kvm_info on initialization failure KVM: arm64: Avoid mismatched accesses to 'struct kvm_nvhe_init_params' s390/vfio-ap: Fix NULL deref in status_show() during queue probe s390/vfio-ap: Fix hot-unplug skipped when last AP adapter or domain removed s390/vfio-ap: fix potential use of uninitialized apm_filtered bitmap s390/vfio-ap: Fix control domain removal in vfio_ap_mdev_cfg_remove s390/vfio-ap: Fix required lock not held during update of ap_matrix_mdev object s390/vfio-ap: Fix missing lock required to access list of ap_matrix_mdev objects s390/vfio-ap: Fix dereference matrix_mdev->kvm without checking for NULL s390/vfio-ap: Fix stale do_remove flag across iterations in vfio_ap_mdev_cfg_remove RISC-V: KVM: fix vcpu vector context handling for kernel-mode vector riscv: vector: allow non-preemptible kernel-mode vector with IRQs off riscv: vector: refactor riscv_v_start_kernel_context KVM: s390: gmap: Make prefix handling optional KVM: s390: gmap: Make CMMA optional KVM: s390: gmap: Make storage keys optional KVM: s390: Prepare gmap for a second KVM implementation ...
2026-08-20Merge tag 'riscv-for-linus-7.3-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley - Add initial definitions and discovery for the Smcsrind, Sscsrind, Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse, Za64rs, and Ssqosid RISC-V ISA extensions - Improve the RISC-V update_mmu_cache_range() implementation by using flush-by-ASID, enabling performance improvements on microarchitectures that support related optimizations; and by taking advantage of the Svinval RISC-V ISA extension on microarchitectures that support it - Shrink CFI shadow stack allocation further (to 512MB) to save virtual address space (and physical memory on systems with strict overcommit policies) - Add initial CPU context switch support for QoS tagging (Ssqosid) - Change our vector misaligned access speed test code to be synchronous, avoiding a bunch of bugs related to unnecessary asynchronicity - Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI table debugging (similar to ARM64 and x86) - Extract vDSO section offsets at build time, rather than run time, to avoid the boot time overhead - Use assembler directives to control the use of instructions from the RISC-V ISA extensions Zacas and Zabha, rather than compiler -march flags that could affect the whole kernel (similar to ARM64) - Add a kselftest for kprobes support for the c.jal instruction on RISC-V - When UEFI runtime services are available, use them to restart and power off - Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing include file to the ACPI code - Move contiguous DMA memory reservation later in the boot, to ensure that the correct global and per-node pools are allocated when CONFIG_CMA_SIZE_PERNUMA is enabled - Disallow probes on breakpoint handlers to avoid recursing indefinitely into do_trap_break() - Patch the compat vDSO during runtime alternatives processing, not only the standard vDSO - Remove some leftover XIP support elements missed by commit 9b3a2be84803 ("riscv: Remove support for XIP kernel") - Fix broadcast timer switching in ACPI LPI power states by implementing a RISC-V version of arch_get_idle_state_flags() - Miscellaneous fixes, including: vDSO makefile simplification; marking our default_power_off() as __noreturn; error path fixes in the PMU SBI perf driver; RISC-V extension capitalization consistency; the use of BIT() macros in one of our include files; and some documentation fixes * tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits) RISC-V: hwprobe: Use BIT macro to avoid warnings riscv: alternative: Also patch the compat vDSO riscv: alternative: Use the statically extracted vDSO section offsets riscv: vdso: Add symbols for the alternative section boundaries riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe riscv: Add Zicclsm to cpufeature and hwprobe riscv: cpufeature: Clarify ISA spec version for canonical order riscv: Standardize extension capitalization riscv: kprobes: Prevent probes in breakpoint handlers riscv: cmpxchg: Use .option arch for Zacas and Zabha riscv: acpi: Handle LPI architectural context loss flags riscv: further remove XIP riscv: Add support for srmcfg CSR from Ssqosid extension riscv: Detect the Ssqosid extension dt-bindings: riscv: Add Ssqosid extension description dt-bindings: riscv: add Counter delegation ISA extensions description RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing RISC-V: Add Ssccfg extension CSR definition dt-bindings: riscv: add Smcntrpmf ISA extension description RISC-V: Add Smcntrpmf extension parsing ...