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2026-10-02dt-bindings: soc: starfive: Add StarFive JHB100 syscon modulesChanghuang Liang
Add documentation to describe StarFive JHB100 SoC System Controller Registers. Add the PLL clocks for the sys0, per0, and per1 domains under syscon, as well as the PCIe RP reset. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-07-19dt-bindings: soc: starfive: Add StarFive syscon moduleWilliam Qiu
Add documentation to describe StarFive System Controller Registers. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>