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5 daysMerge tag 'riscv-for-linus-7.4-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: - Add support for crash hotplug - Improve user copy performance on cores with fast misaligned accesses - Optimize code paths involving pgtable_l{4,5}_enabled() by patching in the return values during early boot (since these don't change during runtime), or by specifying the return values directly in Kconfig files (for purpose-built kernels) - Change the PCIe bus reassignment behavior to depend on the PCI_REASSIGN_ALL_BUS PCI flag (as ARM64 does) - Avoid an unnecessary sstatus CSR read during context switch - Make the sbi_ecall() macro variadic, improving code clarity - Refactor __switch_to_vector() to prepare for upcoming vector context switch optimizations - Add a kselftest for vectorized user copy - Add bounds checking on the shadow stack restore token address to avoid it being used as an attack vector - Fix the shadow stack and indirect branch landing pad control functions to only update the CPU's envcfg CSR when operating on the current task - For MIPS RISC-V systems, add support for early boot-applied errata; and for P8700 RISC-V systems, avoid WFI usage in the kernel (since it is buggy) - Add the "B" RISC-V ISA extension to hwcap and hwprobe reporting - Add support for specifying and reporting the "Zic64b" RISC-V ISA extension, and add it to the SpacemiT K1, K3, and Sophgo SG2044 DT files - Require the block size of cache management operations to be specified in DT schema validation for the RISC-V ISA extensions Zicbom, Zicbop, and Zicboz - Some miscellaneous fixes: fix an incorrect bitfield width in the RVG_SYSTEM_CSR_MASK bitmask macro; make RISCV_ALTERNATIVE mandatory, now that XIP kernel support has been removed; and remove some unnecessary includes in kernel/smp.c * tag 'riscv-for-linus-7.4-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (28 commits) riscv: mm: unexport _pgtable_l4_enabled and _pgtable_l5_enabled riscv: introduce RISCV_ISA_SV48 and RISCV_ISA_SV57 riscv: support early isa ext and use it to optimize pgtable_l4|l5_enabled riscv: convert pgtable_l4|l5_enabled to inline function riscv: remove RISCV_ALTERNATIVE Kconfig option riscv: Add a getter for user PMLEN support riscv: dts: sophgo: sg2044: Add Zic64b ISA extension riscv: dts: spacemit: k1: Add Zic64b ISA extension riscv: dts: spacemit: k3: Add Zic64b ISA extension riscv: Add Zic64b to cpufeature and hwprobe dt-bindings: riscv: Add Zic64b extension description dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz riscv: Add B to hwcap and hwprobe riscv: remove unused profile.h includes riscv: cfi: Only write envcfg CSR when task is current riscv: cfi: Bounds check restore token before swap riscv: Add ERRATA_MIPS_P8700_WFI to replace WFI with mips.pause selftest: riscv: test vectorized user copy riscv: vector: refactor context switch for kernel-mode vector riscv: do not read csr in vector context switch ...
13 daysMerge tag 'soc-dt-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "This is a rather large update of over 1000 non-merge commits touching devicetree files and bindings. A few notable SoC were added this time: - Apple M4 and A18 Pro are used in laptops, these follow the M3 model added in 7.2. - Google Laguna (aka Tensor G5) is used last year's Pixel phone generation. Unlike the earlier Tensor chips, this is not based on Samsung's Exynos family design but starts a new chip family. - Qualcomm's Hawi and Nord SoCs are two powerful chips using the custom Oryon cores. Product names and applications are so far not known, which means that Qualcomm is doing something right by upstreaming kernel support early. The ST stm32mp23xc/stm32mp25xc SoC support was previously removed because there were no users upstream, but they are back now that boards have shown up. Renesas RZ/G2M v3.0 (R8A774A3) is just a minor variation of the already supported SoC. In total, there are 81 new dts files for individual boards, and they are all over the place. Only one riscv based machine is added, the Milk-V Meles SBC using the T-Head th1520 chip. For 32-bit Arm, we have 13 new boards. About half are industrial embedded boards using NXP i.MX6/7 chips, the rest are older products: two Amazon tablets, two Motorola phones and two SoM boards. Everything else is 64-bit Arm: - many industrial embedded boards using NXP layerscape, NXP i.MX8/9, Qualcomm Hamoa, ST stm32mp2, Rockchip rk35xx, and Renesas RZ/G2 SoCs - Laptops and tablets using Apple M4, Qualcomm Snapdragon X2, Snapdragon X1 Elite and Allwinner A133 chips - Valve Steam Frame VR headset using Snapdragon 8 Gen 3 - Seven handheld game consoles using Qualcomm Dragonwing qcs8550 - Mobile phones using Google Tensor G5, Samsung Exynos 850, and various Qualcomm Snapdragon chips Aside from the new stuff, there is still a lot going on for existing socs and boards, including GPU hardware support on MediaTek MT8173 based laptops. Most patches actually add features this time, as the compile-time diagnostic changes are slowing down" * tag 'soc-dt-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1022 commits) arm64: dts: rockchip: Add Radxa E54C dt-bindings: arm: rockchip: Add Radxa E54C arm64: dts: rockchip: remove FRL GPIO for 100ASK DshanPi A1 arm64: dts: rockchip: fix M.2 E-key reset pinctrl on rk3588 rock-5-itx arm64: dts: rockchip: add pcie30phy data-lanes on rk3588 coolpi-cm5-evb arm64: dts: rockchip: Add the fan tachometers to Kobol Helios64 arm64: dts: rockchip: enable NPU on Radxa E52C arm64: dts: rockchip: fix adc button voltage on Radxa E52C riscv: dts: sophgo: sg2002-milkv-duo256m: drop reserved memory node riscv: dts: sophgo: cv1800b-milkv-duo: drop reserved memory node arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes arm64: dts: nuvoton: npcm845-evb: Fix DTS coding style arm64: dts: nuvoton: npcm845: Add peripheral nodes arm64: dts: nuvoton: npcm845: Split APB address ranges riscv: dts: sophgo: cv180x: Fix internal ephy node name riscv: dts: sophgo: add Milk-V Duo 256M ethernet support overlay riscv: dts: sophgo: Limit SG2042 SPI NOR to 12.5 MHz riscv: dts: sophgo: Enable SPI NOR on SRD3-10 riscv: dts: spacemit: set ETH MAC from eeprom for OrangePi arm64: dts: allwinner: sun50i-h616: Add video engine ...
2026-10-08dt-bindings: riscv: Add Zic64b extension descriptionGuodong Xu
Zic64b mandates that cache blocks are 64 bytes in size and naturally aligned in the address space. It is a mandatory extension of both the RVA22 (U64/S64) and RVA23 (U64/S64) profiles, ratified with RISC-V Profiles Version 1.0. Document it so it can be described in the riscv,isa-extensions property, alongside the related Zicbom/Zicbop/Zicboz cache-block extensions. Since Zic64b fixes the cache block size at 64 bytes, also add a schema check requiring any present cbom/cbop/cboz block size to be 64. The check matches only nodes that use riscv,isa-extensions, so nodes carrying just the deprecated riscv,isa string are not affected. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-3-5f14bc5c23d3@oss.qualcomm.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-08dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and ZicbozGuodong Xu
Zicbom, Zicbop, and Zicboz have no default cache block size, so a devicetree that declares one must also provide the matching riscv,cbom/cbop/cboz-block-size property. Make it required so a missing block-size property can be caught by dtbs_check. Match only nodes that use riscv,isa-extensions, so nodes carrying just the deprecated riscv,isa string are not affected. Suggested-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com> Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-2-5f14bc5c23d3@oss.qualcomm.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-10-01dt-bindings: riscv: thead: add Milk-V MelesHan Gao
Document the Milk-V Meles board compatible with the TH1520 fallback. Signed-off-by: Han Gao <gaohan@iscas.ac.cn> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Drew Fustini <fustini@kernel.org> Link: https://patch.msgid.link/20261001-rv-meles-v2-1-c61052262f84@iscas.ac.cn Signed-off-by: Drew Fustini <fustini@kernel.org>
2026-09-01dt-bindings: riscv: cpus: Fix yamllint style issuesJia Wang
Wrap an overlong description line and normalize the inline dependency lists to satisfy yamllint. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260824-ultrarisc-dts-v1-1-61ab7aebe9e5@ultrarisc.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-20Merge tag 'riscv-for-linus-7.3-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley - Add initial definitions and discovery for the Smcsrind, Sscsrind, Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse, Za64rs, and Ssqosid RISC-V ISA extensions - Improve the RISC-V update_mmu_cache_range() implementation by using flush-by-ASID, enabling performance improvements on microarchitectures that support related optimizations; and by taking advantage of the Svinval RISC-V ISA extension on microarchitectures that support it - Shrink CFI shadow stack allocation further (to 512MB) to save virtual address space (and physical memory on systems with strict overcommit policies) - Add initial CPU context switch support for QoS tagging (Ssqosid) - Change our vector misaligned access speed test code to be synchronous, avoiding a bunch of bugs related to unnecessary asynchronicity - Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI table debugging (similar to ARM64 and x86) - Extract vDSO section offsets at build time, rather than run time, to avoid the boot time overhead - Use assembler directives to control the use of instructions from the RISC-V ISA extensions Zacas and Zabha, rather than compiler -march flags that could affect the whole kernel (similar to ARM64) - Add a kselftest for kprobes support for the c.jal instruction on RISC-V - When UEFI runtime services are available, use them to restart and power off - Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing include file to the ACPI code - Move contiguous DMA memory reservation later in the boot, to ensure that the correct global and per-node pools are allocated when CONFIG_CMA_SIZE_PERNUMA is enabled - Disallow probes on breakpoint handlers to avoid recursing indefinitely into do_trap_break() - Patch the compat vDSO during runtime alternatives processing, not only the standard vDSO - Remove some leftover XIP support elements missed by commit 9b3a2be84803 ("riscv: Remove support for XIP kernel") - Fix broadcast timer switching in ACPI LPI power states by implementing a RISC-V version of arch_get_idle_state_flags() - Miscellaneous fixes, including: vDSO makefile simplification; marking our default_power_off() as __noreturn; error path fixes in the PMU SBI perf driver; RISC-V extension capitalization consistency; the use of BIT() macros in one of our include files; and some documentation fixes * tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits) RISC-V: hwprobe: Use BIT macro to avoid warnings riscv: alternative: Also patch the compat vDSO riscv: alternative: Use the statically extracted vDSO section offsets riscv: vdso: Add symbols for the alternative section boundaries riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe riscv: Add Zicclsm to cpufeature and hwprobe riscv: cpufeature: Clarify ISA spec version for canonical order riscv: Standardize extension capitalization riscv: kprobes: Prevent probes in breakpoint handlers riscv: cmpxchg: Use .option arch for Zacas and Zabha riscv: acpi: Handle LPI architectural context loss flags riscv: further remove XIP riscv: Add support for srmcfg CSR from Ssqosid extension riscv: Detect the Ssqosid extension dt-bindings: riscv: Add Ssqosid extension description dt-bindings: riscv: add Counter delegation ISA extensions description RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing RISC-V: Add Ssccfg extension CSR definition dt-bindings: riscv: add Smcntrpmf ISA extension description RISC-V: Add Smcntrpmf extension parsing ...
2026-08-09Merge tag 'tegra-for-7.3-arm64-dt' of ↵Alexandre Belloni
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt arm64: tegra: Device tree changes for v7.3-rc1 This contains a new device tree for the Lenove ThinkEdge SE70 Edge Client device as well as a number of fixes and cleanups for Tegra234 and Tegra194. Tegra264 sees a number of additions to enable more features. * tag 'tegra-for-7.3-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (1469 commits) arm64: tegra: Correct Tegra234 p3740 interrupt flags arm64: tegra: Correct Tegra234 p3737 interrupt flags arm64: tegra: Correct Tegra194 p2972 interrupt flags arm64: tegra: Drop CPU masks from GICv3 PPI interrupts arm64: tegra: Add Lenovo ThinkEdge SE70 device tree arm64: tegra: Add pinctrl nodes for Tegra264 arm64: tegra: Fix CMDQV interrupt type on Tegra264 arm64: tegra: Properly sort devices on Tegra264 arm64: tegra: Add GTE nodes for Tegra264 arm64: tegra: Add Host1x and VIC on Tegra264 arm64: tegra: Populate CPU and L2 cache nodes on Tegra264 arm64: tegra: Enable GPCDMA in Tegra264 and add iommu-map Linux 7.2-rc5 super: fix emergency thaw deadlock on frozen block devices tracing: perf: Fix stale head for perf syscall tracing ftrace: Add global mutex to serialize trace_parser access tracing: Delay module ref count for "enable_event" trigger tracing: Fix use-after-free freeing trigger private data bpf, sockmap: Fix cork use-after-free in tcp_bpf_sendmsg() tracing: Fix context switch counter truncation ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-08-08Merge tag 'spacemit-dt-for-7.3-1' of ↵Alexandre Belloni
https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt RISC-V SpacemiT DT changes for 7.3 For K3 SoC - Enable SD card support - Enable QSPI - Fix reset delay of ETH PHY - Fix PHY ID of ETH - Symbolic PDAM ID - Add SPI controller support - Add USB and PHY support - Add I2S nodes For K1 SoC - Symbolic PDAM ID - Enable cpufreq support - Fix max CPU core voltage For boards of K3 - Pico-ITX - Enable ALDPS on RTL8211F PHY - Disable 125MHz clock on RTL8211F PHY - Enable NOR flash - Add EEPROM support - CoM260 - Add EEPROM support For boards of K1 - Milk-V Jupiter - Enable CPU DVFS - Banana Pi BPI-CM6 - Add initial support - OrangePi R2S - Enable PCIe * tag 'spacemit-dt-for-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (33 commits) riscv: dts: spacemit: Add cpu scaling for Milk-V Jupiter riscv: dts: spacemit: k1-bananapi-cm6: fix maximum CPU core voltage riscv: dts: spacemit: k1-orangepi-r2s: fix maximum CPU core voltage riscv: dts: spacemit: k1-musepi-pro: fix maximum CPU core voltage riscv: dts: spacemit: k1-orangepi-rv2: fix maximum CPU core voltage riscv: dts: spacemit: k1-milkv-jupiter: fix maximum CPU core voltage riscv: dts: spacemit: k1-bananapi-f3: fix maximum CPU core voltage riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 com260 board riscv: dts: spacemit: Make dtschema recognize the etherent PHY correctly on K3 pico-itx board riscv: dts: spacemit: k3: add i2s0-i2s5 nodes riscv: dts: spacemit: k3: add USB controller and USB phy support riscv: dts: spacemit: enable PCIe on OrangePi R2S riscv: dts: spacemit: k3-com260-ifx: add eeprom on i2c1 riscv: dts: spacemit: k3-com260: add eeprom on i2c2 riscv: dts: spacemit: add SPI controllers for K3 riscv: dts: spacemit: add K3 PDMA request numbers riscv: dts: spacemit: Fix phy id check for the phy on com260 board riscv: dts: spacemit: Fix phy id check for the phy on pico-itx board riscv: dts: spacemit: Add enough deassert time for the PHY on com260 board riscv: dts: spacemit: Add enough deassert time for the PHY on PICO ITX ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-08-07dt-bindings: riscv: Add Ssqosid extension descriptionDrew Fustini
Document the ratified Supervisor-mode Quality of Service ID (Ssqosid) extension v1.0. Link: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0 Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Drew Fustini <fustini@kernel.org> Link: https://patch.msgid.link/20260729-dfustini-atl-sc-cbqri-dt-v6-1-7c22b05d461b@kernel.org Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-07dt-bindings: riscv: add Counter delegation ISA extensions descriptionAtish Patra
Add description for the Smcdeleg/Ssccfg extension. Signed-off-by: Atish Patra <atishp@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260807-counter_delegation-v9-10-58658104e487@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-07dt-bindings: riscv: add Smcntrpmf ISA extension descriptionAtish Patra
Add the description for Smcntrpmf ISA extension Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> Link: https://patch.msgid.link/20260807-counter_delegation-v9-7-58658104e487@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-08-07dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptionsAtish Patra
Add the S[m|s]csrind ISA extension description. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Atish Patra <atishp@rivosinc.com> [pjw@kernel.org: use official extension names in the patch description] Link: https://patch.msgid.link/20260807-counter_delegation-v9-4-58658104e487@meta.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-07-24Merge tag 'riscv-dt-for-v7.3-early-k230' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V devicetrees for v7.3 - early k230 material Canaan: Support for the k230 SoC that was too late for the 7.2 window. Consists of some bindings not taken by the various subsystem maintainers, the original dts patches from Yangyu back in 2024 and the more recent clock, reset and pinctrl additions from various contributors. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: canaan: Add clock definition for K230 riscv: dts: canaan: add reset controller for K230 riscv: dts: canaan: k230: Add "b" ISA extension riscv: dts: canaan: Add k230's pinctrl node riscv: dts: canaan: Correct the formatting issues about k230 dts riscv: dts: add initial canmv-k230 and k230-evb dts dt-bindings: interrupt-controller: Add Canaan K230 PLIC dt-bindings: timer: Add Canaan K230 CLINT dt-bindings: add Canaan K230 boards compatible strings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-07-22dt-bindings: riscv: spacemit: Add Banana Pi BPI-CM6 compatibleJunhui Liu
The Banana Pi BPI-CM6 IO board consists of the BPI-CM6 compute module plugged into an IO carrier board, which is used for evaluation and development. The core CM6 module is based on the SpacemiT K1 SoC and provides PMIC, DDR, the eth0 PHY and wireless connectivity. The carrier board extends this by adding the eth1 PHY and external interfaces including Ethernet, PCIe M.2, USB, MicroSD, QSPI, and serial console connectivity. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260712-bpi-cm6-v3-1-8d1e2045179d@pigmoral.tech Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-07-08dt-bindings: riscv: sort multi-letter Z extensions alphanumericallyGuodong Xu
The multi-letter extension enum is documented as being sorted alphanumerically (see the "multi-letter extensions, sorted alphanumerically" comment), but several Z entries have drifted out of order. Reorder the affected entries so the multi-letter Z list is sorted alphanumerically again. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Link: https://patch.msgid.link/20260701-rva23u64-hwprobe-v2-v5-1-2c61f94a695a@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-06-14dt-bindings: add Canaan K230 boards compatible stringsYangyu Chen
Since K230 was released, K210 is no longer the only SoC in the Kendryte series, so remove the K210 string from the description. Also, add two boards based on k230 to compatible strings to allow them to be used in the dt. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-05-29dt-bindings: riscv: spacemit: Add K3 CoM260-IFX boardYixun Lan
The SpacemiT K3 CoM260-IFX board combines a 69.6 × 45 mm compute module with a reference carrier board. The module integrates up to 32GB LPDDR5 memory, UFS storage, Micro SD card slot and includes interfaces such as dual MIPI CSI-2 connectors, M.2 expansion, USB 3.0, Gigabit Ethernet, DisplayPort, and a 40-pin expansion header. The carrier board is intended as a general-purpose development platform for CoM260 module and exposes interfaces for all of storage, display, networking, and camera connectivity. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260520-02-k3-com260-ifx-v2-1-d55095457cf0@kernel.org Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-04-27dt-bindings: riscv: spacemit: add deepcomputing,fml13v05Sandie Cao
Document the compatible string for the Deepcomputing fml13v05. It's based on the SpacemiT K3 RISC-V SoC and is designed for the Framework Laptop 13 Chassis, which has (Framework) SKU FRANHQ0001. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Sandie Cao <sandie.cao@deepcomputing.io> Reviewed-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://lore.kernel.org/r/20260421064200.1582367-1-sandie.cao@deepcomputing.io Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-03-24dt-bindings: riscv: Add Supm extension descriptionGuodong Xu
Add description for the Supm extension. Supm indicates support for pointer masking in user mode. Supm is mandatory for RVA23S64. Add dependency check that Supm requires either Smnpm or Ssnpm. The Supm extension is ratified in commit d70011dde6c2 ("Update to ratified state") of riscv-j-extension. Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-03-24dt-bindings: riscv: microchip: document the PIC64GX curiosity kitPierre-Henry Moussay
Update devicetree bindings document with PIC64GX Curiosity Kit, known by its "Curiosity-GX1000" product code. Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-02-12Merge tag 'riscv-for-linus-7.0-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: - Add support for control flow integrity for userspace processes. This is based on the standard RISC-V ISA extensions Zicfiss and Zicfilp - Improve ptrace behavior regarding vector registers, and add some selftests - Optimize our strlen() assembly - Enable the ISO-8859-1 code page as built-in, similar to ARM64, for EFI volume mounting - Clean up some code slightly, including defining copy_user_page() as copy_page() rather than memcpy(), aligning us with other architectures; and using max3() to slightly simplify an expression in riscv_iommu_init_check() * tag 'riscv-for-linus-7.0-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (42 commits) riscv: lib: optimize strlen loop efficiency selftests: riscv: vstate_exec_nolibc: Use the regular prctl() function selftests: riscv: verify ptrace accepts valid vector csr values selftests: riscv: verify ptrace rejects invalid vector csr inputs selftests: riscv: verify syscalls discard vector context selftests: riscv: verify initial vector state with ptrace selftests: riscv: test ptrace vector interface riscv: ptrace: validate input vector csr registers riscv: csr: define vtype register elements riscv: vector: init vector context with proper vlenb riscv: ptrace: return ENODATA for inactive vector extension kselftest/riscv: add kselftest for user mode CFI riscv: add documentation for shadow stack riscv: add documentation for landing pad / indirect branch tracking riscv: create a Kconfig fragment for shadow stack and landing pad support arch/riscv: add dual vdso creation logic and select vdso based on hw arch/riscv: compile vdso with landing pad and shadow stack note riscv: enable kernel access to shadow stack memory via the FWFT SBI call riscv: add kernel command line option to opt out of user CFI riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe ...
2026-01-28Merge tag 'riscv-dt-for-v6.20' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.20 (or v7.0) Anlogic: Minor change to the extension information, to add the "b" extension that's a catch-all for 3 of the extensions already in the dts. Starfive: Append the jh7110 compatible to jh7110s devicetrees, as that will enable OpenSBI etc to run without adding support for this minor variant. The "s" device differs from the non "s" device only in thermal limits and voltage/frequency characteristics. Microchip: Redo the mpfs clock setup yet again, to something approaching correct. The original binding conjured up for the platform was wildly inaccurate, and even with the original improvements, a bigger change to using syscons was required to support several peripherals that also inhabit the memory regions that the clocks lie in. The damage to the dts isn't that bad in the end, and of course the whole thing has been done in a backwards compatible manner, with the code changes being merged a cycle or two ago in the kernel and like a year ago in U-Boot (the only other user that I am aware of). Generic: Additions to extensions.yaml, mainly for things in the "rva23" profile that appear for the first time on the Spacemit K3 SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: anlogic: dr1v90: Add "b" ISA extension dt-bindings: riscv: extensions: Drop unnecessary select schema dt-bindings: riscv: Add Sha and its comprised extensions dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm dt-bindings: riscv: Add B ISA extension description dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board riscv: dts: microchip: convert clock and reset to use syscon riscv: dts: microchip: fix mailbox description Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-28Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux ↵Arnd Bergmann
into soc/dt RISC-V SpacemiT DT changes for 6.20 - Disable Ethernet PHY auto sleep mode - Add pinctrl IO power support - Add K3 Pico-ITX board - Add support for K3 SoC - Add DWC USB support - Add reset for eMMC(sdhci)/I2C - Add PCIe support - Support PMIC for Jupiter board * tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux: riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi riscv: dts: spacemit: pinctrl: update register and IO power riscv: dts: spacemit: add K3 Pico-ITX board support riscv: dts: spacemit: add initial support for K3 SoC dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC dt-bindings: interrupt-controller: add SpacemiT K3 APLIC dt-bindings: timer: add SpacemiT K3 CLINT dt-bindings: riscv: add SpacemiT X100 CPU compatible riscv: dts: spacemit: k1: Add "b" ISA extension riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3 riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1 riscv: dts: spacemit: Add USB2 PHY node for K1 riscv: dts: spacemit: sdhci: add reset support riscv: dts: spacemit: add reset property riscv: dts: spacemit: PCIe and PHY-related updates riscv: dts: spacemit: Add a PCIe regulator riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-01-25dt-bindings: riscv: document zicfilp and zicfiss in extensions.yamlDeepak Gupta
Make an entry for cfi extensions in extensions.yaml. Signed-off-by: Deepak Gupta <debug@rivosinc.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Andreas Korb <andreas.korb@aisec.fraunhofer.de> # QEMU, custom CVA6 Tested-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Link: https://patch.msgid.link/20251112-v5_user_cfi_series-v23-2-b55691eacf4f@rivosinc.com [pjw@kernel.org: updated subject] Signed-off-by: Paul Walmsley <pjw@kernel.org>
2026-01-20dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindingsGuodong Xu
Add DT binding documentation for the SpacemiT K3 SoC and the board Pico-ITX which is a 2.5-inch single-board computer. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-5-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-20dt-bindings: riscv: add SpacemiT X100 CPU compatibleGuodong Xu
Add compatible string for the SpacemiT X100 core. [1] The X100 is a 64-bit RVA23-compliant RISC-V core from SpacemiT. X100 supports the RISC-V vector and hypervisor extensions and all mandatory extersions as required by the RVA23U64 and RVA23S64 profiles, per the definition in 'RVA23 Profile, Version 1.0'. [2] From a microarchieture viewpoint, the X100 features a 4-issue out-of-order pipeline. X100 is used in SpacemiT K3 SoC. Acked-by: Paul Walmsley <pjw@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://www.spacemit.com/en/spacemit-x100-core/ [1] Link: https://docs.riscv.org/reference/profiles/rva23/_attachments/rva23-profile.pdf [2] Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Link: https://lore.kernel.org/r/20260115-k3-basic-dt-v5-1-6990ac9f4308@riscstar.com Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-01-13dt-bindings: riscv: extensions: Drop unnecessary select schemaRob Herring (Arm)
The "select" schema is not necessary because this schema is referenced by riscv/cpus.yaml schema. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-13dt-bindings: riscv: Add Sha and its comprised extensionsGuodong Xu
Add descriptions for the Sha extension and the seven extensions it comprises: Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen. Sha is ratified in the RVA23 Profiles Version 1.0 (commit 0273f3c921b6 "rva23/rvb23 ratified") as a new profile-defined extension that captures the full set of features that are mandated to be supported along with the H extension. Extensions Shcounterenw, Shgatpa, Shtvala, Shvsatpa, Shvstvala, Shvstvecd, and Ssstateen are ratified in the RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state"). The requirement status for Sha and its comprised extension in RISC-V Profiles are: - Sha: Mandatory in RVA23S64 - H: Optional in RVA22S64; Mandatory in RVA23S64 - Shcounterenw: Optional in RVA22S64; Mandatory in RVA23S64 - Shgatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shtvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvsatpa: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvala: Optional in RVA22S64; Mandatory in RVA23S64 - Shvstvecd: Optional in RVA22S64; Mandatory in RVA23S64 - Ssstateen: Optional in RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-13dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xlGuodong Xu
Add descriptions for five new extensions: Ssccptr, Sscounterenw, Sstvala, Sstvecd, and Ssu64xl. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, their requirement status are: - Ssccptr: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sscounterenw: Mandatory in RVA22S64, RVA23S64 - Sstvala: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Sstvecd: Mandatory in RVA20S64, RVA22S64, RVA23S64 - Ssu64xl: Optional in RVA20S64, RVA22S64; Mandatory in RVA23S64 Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-13dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and ZicclsmGuodong Xu
Add descriptions for four extensions: Za64rs, Ziccamoa, Ziccif, and Zicclsm. These extensions are ratified in RISC-V Profiles Version 1.0 (commit b1d806605f87 "Updated to ratified state."). They are introduced as new extension names for existing features and regulate implementation details for RISC-V Profile compliance. According to RISC-V Profiles Version 1.0 and RVA23 Profiles Version 1.0, they are mandatory for the following profiles: - za64rs: Mandatory in RVA22U64, RVA23U64 - ziccamoa: Mandatory in RVA20U64, RVA22U64, RVA23U64 - ziccif: Mandatory in RVA20U64, RVA22U64, RVA23U64 - zicclsm: Mandatory in RVA20U64, RVA22U64, RVA23U64 Ziccrse specifies the main memory must support "RsrvEventual", which is one (totally there are four) of the support level for Load-Reserved/ Store-Conditional (LR/SC) atomic instructions. Thus it depends on Zalrsc. Ziccamoa specifies the main memory must support AMOArithmetic, among the four levels of PMA support defined for AMOs in the A extension. Thus it depends on Zaamo. Za64rs defines reservation sets are contiguous, naturally aligned, and a maximum of 64 bytes. Za64rs is consumed by two extensions: Zalrsc and Zawrs. Zawrs itself depends on Zalrsc too. Based on the relationship that "A" = Zaamo + Zalrsc, add the following dependencies checks: Za64rs -> Zalrsc or A Ziccrse -> Zalrsc or A Ziccamoa -> Zaamo or A Signed-off-by: Guodong Xu <guodong@riscstar.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-13dt-bindings: riscv: Add B ISA extension descriptionGuodong Xu
Add description of the single-letter B extension for Bit Manipulation. B is mandatory for RVA23U64. The B extension is ratified in the 20240411 version of the unprivileged ISA specification. According to the ratified spec, the B standard extension comprises instructions provided by the Zba, Zbb, and Zbs extensions. Add two-way dependency check to enforce that B implies Zba/Zbb/Zbs; and when Zba/Zbb/Zbs (all of them) are specified, then B must be added too. The reason why B/Zba/Zbb/Zbs must coexist at the same time is that unlike other single-letter extensions, B was ratified (Apr/2024) much later than its component extensions Zba/Zbb/Zbs (Jun/2021). When "b" is specified, zba/zbb/zbs must be present to ensure backward compatibility with existing software and kernels that only look for the explicit component strings. When all three components zba/zbb/zbs are specified, "b" should also be present. Making "b" mandatory when all three components are present. Existing devicetrees with zba/zbb/zbs but without "b" will generate warnings that can be fixed in follow-up patches. Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-01-13dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmtGuodong Xu
The descriptions for h, svinval, svnapot, and svpbmt extensions currently reference the "20191213 version of the privileged ISA specification". While an Unprivileged ISA document exists with that date, there is no corresponding ratified Privileged ISA specification. These extensions were ratified in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20211203. Update the descriptions to reference the correct specification version. RISC-V International hosts a website [1] for ratified specifications. Following the "Ratified ISA Specifications", historical versions of Volume II Privileged ISA can be found. Link: https://riscv.org/specifications/ratified/ [1] Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <guodong@riscstar.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-20dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 ↵E Shattow
Lite board Append "starfive,jh7110" compatible to VisionFive 2 Lite and VisionFive 2 Lite eMMC boards in the least-compatible end of the list. Appending "starfive,jh7110" reduces the number of compatible strings to check in the OpenSBI platform driver. JH-7110S SoC on these boards is the same as JH-7110 SoC however rated for thermal, voltage, and frequency characteristics for a maximum of 1.25GHz operation. Link: https://lore.kernel.org/lkml/1f96a267-f5c6-498e-a2c4-7a47a73ea7e7@canonical.com/ Suggested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: E Shattow <e@freeshell.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-12-19dt-bindings: riscv: add Zilsd and Zclsd extension descriptionsPincheng Wang
Add descriptions for the Zilsd (Load/Store pair instructions) and Zclsd (Compressed Load/Store pair instructions) ISA extensions which were ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> Reviewed-by: Nutty Liu <nutty.liu@hotmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20250826162939.1494021-2-pincheng.plct@isrc.iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-05Merge tag 'soc-newsoc-6.19' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull new SoC families update from Arnd Bergmann: "These three new families of SoC are split out into a separate branch because they touch multiple parts of the source tree and are better left separate for the initial merge. - Black Sesame Technologies C1200 is an automotive SoC using Cortex-A78 CPU cores - Anlogic dr1v90 (not to be confused with Amlogic) is an FPGA platform using a single nuclei ux900 RISC-V core - Tenstorrent Blackhole is a Neural Processing Unit using custom "Tensix" cores for computation offload managed by Linux running on SiFive X280 RISC-V cores. Support for all three is rather rudimentary at the moment and will get improved as device drivers are merged through other tree" * tag 'soc-newsoc-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (24 commits) MAINTAINERS: add Black Sesame Technologies (BST) ARM SoC support arm64: defconfig: enable BST platform support arm64: dts: bst: add support for Black Sesame Technologies C1200 CDCU1.0 board arm64: Kconfig: add ARCH_BST for Black Sesame Technologies SoCs dt-bindings: arm: add Black Sesame Technologies (bst) SoC dt-bindings: vendor-prefixes: Add Black Sesame Technologies Co., Ltd. MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei riscv: defconfig: Enable Tenstorrent SoCs riscv: Kconfig.socs: Add ARCH_TENSTORRENT for Tenstorrent SoCs riscv: dts: Add Tenstorrent Blackhole SoC PCIe cards dt-bindings: interrupt-controller: Add Tenstorrent Blackhole compatible ...
2025-12-05Merge tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "Three new SoCs got added in existing arm64 chip families: - Renesas R-Car X5H (R8A78000) is a new generation of automotive SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the currently highest-perforance embedded SoC. - TI AM62L is a new variant of the AM62 family of industrial SoCs, this one comes without a GPU. - Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip based on Cortex-A53, and closely related to MSM8917 (Snapdragn 425), which we already support. In addition, there are a good number of newly supported machines across SoC families: - Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers - Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124, Qualcomm MSM8937 and Qualcomm MSM8939, - Two Laptops based on Qualcomm SoCs: one using the older sdm850, the other using x1p42100. - One Router based on Rockchips RK3568 - 24 variants of the Enclustra Mercury system-on-module, all based on 32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit SocFPGA Agilex chips.. - 30 industrial/embedded boards and single-board computers, using various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm, Spacemit, and Starfive. In total there are 783 commits here, the majority of these improving hardware support and cleaning up devicetree files across the tree, with the majority of the changes going into the Qualcomm, NXP, Renesas and Rockchips platforms" * tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits) arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1 ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs arm64: dts: Add gpio_intc node for Amlogic S7D SoCs arm64: dts: Add gpio_intc node for Amlogic S7 SoCs arm64: dts: Add gpio_intc node for Amlogic S6 SoCs arm64: dts: amlogic: s7d: add ao secure node arm64: dts: amlogic: s7: add ao secure node arm64: dts: amlogic: s6: add ao secure node arm64: dts: amlogic: Fix the register name of the 'DBI' region dts: arm64: amlogic: add a5 pinctrl node arm64: dts: amlogic: s7d: add power domain controller node arm64: dts: amlogic: s7: add power domain controller node arm64: dts: amlogic: s6: add power domain controller node dts: arm64: amlogic: Add ISP related nodes for C3 arm64: dts: meson: add initial device-tree for Tanix TX9 Pro dt-bindings: arm: amlogic: add support for Tanix TX9 Pro ...
2025-12-05Merge tag 'riscv-for-linus-6.19-mw1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Paul Walmsley: - Enable parallel hotplug for RISC-V - Optimize vector regset allocation for ptrace() - Add a kernel selftest for the vector ptrace interface - Enable the userspace RAID6 test to build and run using RISC-V vectors - Add initial support for the Zalasr RISC-V ratified ISA extension - For the Zicbop RISC-V ratified ISA extension to userspace, expose hardware and kernel support to userspace and add a kselftest for Zicbop - Convert open-coded instances of 'asm goto's that are controlled by runtime ALTERNATIVEs to use riscv_has_extension_{un,}likely(), following arm64's alternative_has_cap_{un,}likely() - Remove an unnecessary mask in the GFP flags used in some calls to pagetable_alloc() * tag 'riscv-for-linus-6.19-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: selftests/riscv: Add Zicbop prefetch test riscv: hwprobe: Expose Zicbop extension and its block size riscv: Introduce Zalasr instructions riscv: hwprobe: Export Zalasr extension dt-bindings: riscv: Add Zalasr ISA extension description riscv: Add ISA extension parsing for Zalasr selftests: riscv: Add test for the Vector ptrace interface riscv: ptrace: Optimize the allocation of vector regset raid6: test: Add support for RISC-V raid6: riscv: Allow code to be compiled in userspace raid6: riscv: Prevent compiler from breaking inline vector assembly code riscv: cmpxchg: Use riscv_has_extension_likely riscv: bitops: Use riscv_has_extension_likely riscv: hweight: Use riscv_has_extension_likely riscv: checksum: Use riscv_has_extension_likely riscv: pgtable: Use riscv_has_extension_unlikely riscv: Remove __GFP_HIGHMEM masking RISC-V: Enable HOTPLUG_PARALLEL for secondary CPUs
2025-11-27Merge tag 'riscv-dt-for-v6.19' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.19 MAINTAINERS: There's some re-jigging of things to reduce duplication, by moving me into the StarFive entry and my tree into the Microchip one. The other platforms that I look after (SiFive and Canaan) are marked as Odd Fixes to better represent their status. Nothing functionally changes. Microchip: Add adc and mmc nodes for the Beagle-V Fire. SiFive: Add pwm fans to the unmatched board. StarFive: Add the Orange PI RV board, another VisionFive 2 derived SBC. This required moving a mmc related nodes out of the common file, into <board>.dts. Yet more things moved out of the common file when the VisionFive 2 Lite boards were added, which use the JH7110S SoC instead of the JH7110. The difference here between SoCs is just temperature and frequency ranges, but the boards differ enough that the pool of common nodes decreases a little further. There's an eMMC and an SD variant here, that are different SKUs, bringing the total new StarFive boards to three. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.19' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: add Orange Pi RV dt-bindings: riscv: starfive: add xunlong,orangepi-rv riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree riscv: dts: starfive: Add VisionFive 2 Lite board device tree riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes MAINTAINERS: add tree to RISC-V Microchip entry MAINTAINERS: remove patchwork from RISC-V MISC SOC SUPPORT MAINTAINERS: add Conor to StarFive entry riscv: dts: sifive: unmatched: Add PWM controlled fans riscv: dts: microchip: enable qspi adc/mmc-spi-slot on BeagleV Fire dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-11-25dt-bindings: riscv: starfive: add xunlong,orangepi-rvIcenowy Zheng
Add "xunlong,orangepi-rv" as a StarFive JH7110 SoC-based board. Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Signed-off-by: E Shattow <e@freeshell.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-25dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite boardHal Feng
Add device tree bindings for the StarFive JH7110S SoC and the VisionFive 2 Lite board equipped with it. JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade and up to 1.25GHz. Its CPU cores and peripherals are the same as those of the JH7110 SoC. VisionFive 2 Lite boards have MicroSD card version (default) and eMMC version, which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC" respectively. Acked-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Matthias Brugger <mbrugger@suse.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-24dt-bindings: riscv: Add Svrsw60t59b extension descriptionChunyan Zhang
Add description for the Svrsw60t59b extension (PTE Reserved for SW bits 60:59) extension which was ratified recently in riscv-non-isa/riscv-iommu. Link: https://lkml.kernel.org/r/20251113072806.795029-7-zhangchunyan@iscas.ac.cn Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chunyan Zhang <zhangchunyan@iscas.ac.cn> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Alexandre Ghiti <alexghiti@rivosinc.com> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: Andrew Jones <ajones@ventanamicro.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Axel Rasmussen <axelrasmussen@google.com> Cc: Christian Brauner <brauner@kernel.org> Cc: Conor Dooley <conor@kernel.org> Cc: David Hildenbrand <david@redhat.com> Cc: Deepak Gupta <debug@rivosinc.com> Cc: Jan Kara <jack@suse.cz> Cc: Liam Howlett <liam.howlett@oracle.com> Cc: Lorenzo Stoakes <lorenzo.stoakes@oracle.com> Cc: Michal Hocko <mhocko@suse.com> Cc: Mike Rapoport <rppt@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Peter Xu <peterx@redhat.com> Cc: Rob Herring <robh@kernel.org> Cc: Suren Baghdasaryan <surenb@google.com> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Yuanchu Xie <yuanchu@google.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
2025-11-21Merge tag 'anlogic-initial-6.19-v2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/newsoc Initial Anlogic Platform Support Add bindings for the serial and timer peripherals, and a basic soc dtsi for the Anlogic dr1v90 SoC. The Milianke MLKPAI FS01 is the first board for this SoC. Add myself as maintainer for this platform for the time being. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'anlogic-initial-6.19-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: Setup support for Anlogic tree riscv: defconfig: Enable Anlogic SoC riscv: dts: anlogic: Add Milianke MLKPAI FS01 board riscv: dts: Add initial Anlogic DR1V90 SoC device tree riscv: Add Anlogic SoC famly Kconfig support dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart dt-bindings: timer: Add Anlogic DR1V90 ACLINT MTIMER dt-bindings: riscv: Add Anlogic DR1V90 dt-bindings: riscv: Add Nuclei UX900 compatibles dt-bindings: vendor-prefixes: Add Anlogic, Milianke and Nuclei
2025-11-19dt-bindings: riscv: Add Zalasr ISA extension descriptionXu Lu
Add description for the Zalasr ISA extension Signed-off-by: Xu Lu <luxu.kernel@bytedance.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251020042056.30283-3-luxu.kernel@bytedance.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-11-12dt-bindings: riscv: Add Anlogic DR1V90Junhui Liu
Add Anlogic DR1V90 FPSoC, featuring a UX900 RISC-V core as the processing system (PS) and 94,464 LUTs programmable logic (PL). It is used by the Milianke MLKPAI-FS01 board, a SBC equipped with 512MB DDR3 memory, USB-C UART, 1GbE RJ45 Ethernet, USB-A 2.0 port, TF card slot, and 256Mbit Quad-SPI flash. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-12dt-bindings: riscv: Add Nuclei UX900 compatiblesJunhui Liu
The UX900 is a RISC-V core from Nuclei, used in the Anlogic DR1V90 SoC. It features a 64-bit architecture and dual-issue, 9-stage pipeline, with lots of optional extensions including V, K, Zc, and more. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2025-11-12dt-bindings: riscv: spacemit: Add OrangePi R2S boardMichael Opdenacker
Document the compatible string for the OrangePi R2S board [1], which is marketed as using the Ky X1 SoC but is in fact identical in die and package to the SpacemiT K1 SoC [2]. Link: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/details/Orange-Pi-R2S.html [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Signed-off-by: Michael Opdenacker <michael.opdenacker@rootcommit.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20251112044426.2351999-2-michael.opdenacker@rootcommit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-11-06dt-bindings: riscv: spacemit: add MusePi Pro boardTroy Mitchell
Document the compatible string for the MusePi Pro [1]. It is a 1.8-inch single board computer based on the SpacemiT K1/M1 RISC-V SoC [2]. Here's a refined list of its core features: - SoC: SpacemiT M1/K1, 8-core 64-bit RISC-V. - Memory: LPDDR4X @ 2400MT/s, available in 8GB & 16GB options. - Storage: Onboard eMMC 5.1 (64GB/128GB options), M.2 M-Key for NVMe SSD (2230 size), and a microSD slot (UHS-II) for expansion. - Display: HDMI 1.4 (1080P@60Hz) and 2-lane MIPI DSI FPC (1080P@60Hz). - Connectivity: Onboard Wi-Fi 6 & Bluetooth 5.2, single Gigabit Ethernet port (RJ45). - USB: 4x USB 3.0 Type-A (host) and 1x USB 2.0 Type-C (device/OTG). - Expansion: Full-size miniPCIe slot and a second M.2 M-Key (2230). - GPIO: Standard 40-pin GPIO interface. - MIPI: 1x 4-lane MIPI CSI FPC and 2x MIPI DSI FPC interfaces. - Clock: Onboard RTC with battery support. Link: https://developer.spacemit.com/documentation?token=YJtdwnvvViPVcmkoPDpcvwfVnrh&type=pdf [1] Link: https://www.spacemit.com/en/key-stone-k1 [2] Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Troy Mitchell <troy.mitchell@linux.spacemit.com> Link: https://lore.kernel.org/r/20251023-k1-musepi-pro-dts-v4-1-01836303e10f@linux.spacemit.com Signed-off-by: Yixun Lan <dlan@gentoo.org>
2025-10-18dt-bindings: riscv: cpus: Add SiFive X280 compatibleDrew Fustini
Document compatible for the SiFive X280 RISC-V core. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>
2025-10-18dt-bindings: riscv: Add Tenstorrent Blackhole compatibleDrew Fustini
Add compatibles for the Tenstorrent Blackhole SoC PCIe card. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Joel Stanley <jms@oss.tenstorrent.com> Signed-off-by: Drew Fustini <dfustini@oss.tenstorrent.com>