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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- A bunch of improvements in dt-check-style. Fix various bindings based
on these additional checks.
- Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade,
hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs,
mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and
ti,omap-ocp2scp to DT schema format
- Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO
PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus,
HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC
- Various binding updates to fix schema warnings in .dts files
- Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and
regulator, and mailbox.txt
- Remove the unused of_overlay_remove_all() function
- Fixes for of_check_msi_parent()
- Add "i2c-parent" tracking to fw_devlink
* tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits)
dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller
dt-bindings: iommu: Describe MT8195 infra IRQs
dt-bindings: clock: mediatek: Add MT8516 fallbacks
dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema
dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema
dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema
dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY
of: overlay: remove unused of_overlay_remove_all()
dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema
dt-bindings: bus: Add HiSilicon local bus
dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu
dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC
dt-bindings: vendor-prefixes: add Ambarella
dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings
dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints
dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema
dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema
of/irq: Stop the MSI walk at the first msi-parent
of/irq: Fix device node refcount leak in of_check_msi_parent()
dt-bindings: display: faraday,tve200: Use a level-high interrupt
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are lots of minor updates for driver subsystems managed through
the soc tree (turris-omnia platform, cache driver, tee drivers,
arm-cci, bus, memory) as well as soc vendor specific drivers
(starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti,
nvidia).
The more notable changes are:
- Larger updates for Qualcomm SoCs including support for SM8950
(Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424
- Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and
MT8167 in existing drivers
- Arm SCMI firmware driver support for ACPI PCC transport and module
autoloading of protocol specific drivers
- Apple crash log support for CrgA embedded controller"
* tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits)
platform: cznic: turris-omnia-mcu: stop button emulation producers
cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers
soc: mpfs: use kref cleanup on probe failure
arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms
bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port()
bus: arm-cci: Drop CPU node reference in cci_ace_init_ports()
soc: fsl: dpio: Free the IRQ before releasing the I/O object
soc: fsl: dpio: Fix cleanup on IRQ registration failure
bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr
bus: fsl-mc: drop the fwnode links of the dpmacs nodes
soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms()
soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get()
firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7
dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller
dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC
soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove
ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
firmware: qcom: tzmem: disable SHM bridge for SM7125 platform
soc: qcom: ubwc: Add Kalambo UBWC config
firmware: qcom: scm: Allow QSEECOM on Kalambo CRD
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Document the APCS mailbox compatible for the IPQ9650 SoC. IPQ9650 uses
qcom,msm8994-apcs-kpss-global as a fallback, so add the valid compatible
string combination to the binding.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Convert the hisilicon,hi6220-mbox binding to DT schema format. It's a
straight forward conversion.
Assisted-by: LLM
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Convert the hisilicon,hi3660-mbox binding to DT schema format. The
binding and driver give no clue about what the 2 interrupts are, so more
details can't be added.
Assisted-by: LLM
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Add the compatible for the APCS in the SDM670 SoC.
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Add the ti,tda54-main-secure-proxy compatible for the secure proxy
mailbox controller integrated in the MAIN voltage domain of the TI TDA54
SoC, which features up to 444 threads with 60-byte messages per
thread.
The number of threads is fixed at SoC integration and cannot be
discovered at runtime, therefore a separate compatible is needed.
Signed-off-by: Beleswar Padhi <b-padhi@ti.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document the CPU Control Processor (CPUCP) mailbox controller for the
Qualcomm Maili SoC. It is software compatible with the X1E80100 CPUCP
mailbox controller and uses it as a fallback compatible string.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Maria Yu <aiqun.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260907-maili_initial_clock-v5-1-e79bb6b93a49@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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As per mailing-list discussions [1] [2] [3], we want to delete the
following old file from the device-tree bindings that live in the
Linux kernel git tree:
* Documentation/devicetree/bindings/mailbox/mailbox.txt
The old .txt file did have some descriptive text about what some of
the properties meant. Those have been added to the dt-schema
repository in a pull request [4].
Also remove dangling references to `mailbox.txt` across all remaining
device-tree binding documentation files.
Link: https://lore.kernel.org/r/20260722140214.GA548057-robh@kernel.org [1]
Link: https://lore.kernel.org/r/dc7a2041-50a4-482e-9930-566bb3fd1e72@kernel.org [2]
Link: https://lore.kernel.org/r/CAL_JsqKVjQ2m-dzMUENQry-f_YE9QrYSOKoH9CPj1gjj8XkPRA@mail.gmail.com [3]
Link: https://github.com/devicetree-org/dt-schema/pull/202 [4]
Cc: Sudeep Holla <sudeep.holla@kernel.org>
Cc: Jassi Brar <jassisinghbrar@gmail.com>
Cc: Lee Jones <lee@kernel.org>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://patch.msgid.link/20260814124603.v2.1.I8b3ff71c528133e7d6f81fe926fa39e6451d63fd@changeid
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar:
- mhuv2:
- convert channel translation to fw_xlate()
- use generic device property APIs
- axiado:
- add AX3005 mailbox controller driver and DT bindings
- bcm2835:
- use platform_get_irq()
- simplify probe error handling
- cix:
- fix DT property string typo
- use dev_err_probe()
- exynos:
- add Exynos850 mailbox driver support and DT bindings
- microchip:
- add null check for devm_kasprintf()
- pcc:
- fix missed-interrupt command timeout
- verify shared memory signature
- notify clients on polled completion
- qcom:
- fix CPUCP PREEMPT_RT deadlock and NULL data crash
- fix IPCC duplicate channel allocation across holes
- add IPQ5210 APCS and Nord IPCC bindings
- riscv:
- validate RPMI notification buffer lengths and event payload bounds
- rockchip:
- manage peripheral clock with devm helper
- drop unused struct field
- ti-msgmgr:
- convert bindings to DT schema
- remove redundant dev_err()/dev_err_probe() on IRQ request failures
across drivers
* tag 'mailbox-v7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: (22 commits)
mailbox: add Axiado AX3005 mailbox driver
dt-bindings: mailbox: add Axiado AX3005 mailbox
dt-bindings: mailbox: Convert TI Message Manager to DT schema
mailbox: cix: fix DT property name string typo and use dev_err_probe()
mailbox: riscv-sbi-mpxy: validate RPMI notification lengths
mailbox: bcm2835: use platform_get_irq and simplify probe
mailbox: qcom-ipcc: fix duplicate channel allocation across holes
mailbox: mchp-ipc-sbi: Add null check for devm_kasprintf()
mailbox: Remove redundant dev_err()/dev_err_probe()
dt-bindings: mailbox: qcom: Add IPQ5210 APCS compatible
dt-bindings: mailbox: qcom-ipcc: Document Nord IPCC
mailbox: exynos: Add support for Exynos850 mailbox
dt-bindings: mailbox: google,gs101-mbox: Add samsung,exynos850-mbox
mailbox: pcc: Fix command timeout due to missed interrupt
mailbox: pcc: Check shared memory signature on request
mailbox: pcc: Notify clients on polled completion
mailbox: rockchip: drop unneeded runtime pointer (pclk)
mailbox: rockchip: disable pclk on probe failure and unbind
mailbox: qcom-cpucp: handle NULL data in send_data callback
mailbox: qcom-cpucp: fix PREEMPT_RT self-deadlock in IRQ handler
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Add a devicetree binding for the Axiado AX3005 mailbox controller.
The controller provides inter-processor communication channels
between the host CPU and the coprocessor, with separate TX and RX
register regions.
Add the corresponding MAINTAINERS entry covering the binding.
Signed-off-by: Swark Yang <syang@axiado.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Convert the Texas Instruments Message Manager binding
to DT schema.
Signed-off-by: Eduard Bostina <egbostina@gmail.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Add the APCS mailbox compatible for the IPQ5210 SoC. It uses the IPQ6018
APCS mailbox compatible as a fallback, so document the valid compatible
string combination in the binding.
Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document Inter-Processor Communication Controller on Qualcomm Nord SoC.
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document support for a mailbox present on Exynos850-based platforms.
The registers offsets are different from gs101 mailbox, but the
workflow is similar, hence new compatible.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style. No
functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Acked-by: Jeff Johnson <jjohnson@kernel.org> # qcom,ath10k.yaml
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for Documentation/devicetree/bindings/pwm
Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://patch.msgid.link/20260801195613.235430-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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MAINTAINERS disagrees with Documentation/devicetree/bindings on Sudeep's
email address; fix the latter.
Fixes: 59e82a4237cf ("MAINTAINERS: Change Sudeep Holla's email address")
Signed-off-by: Laszlo Ersek <laszlo.ersek@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@kernel.org>
Link: https://patch.msgid.link/20260720160235.36592-1-laszlo.ersek@arm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Document the Inter-Processor Communication Controller on the Qualcomm
Maili Platform, which will be used to route interrupts across various
subsystems found on the SoC.
Signed-off-by: Chunkai Deng <chunkai.deng@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document the Inter-Processor Communication Controller on the Qualcomm
Hawi Platform, which will be used to route interrupts across various
subsystems found on the SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm
Hawi SoCs. It is software compatible with X1E80100 CPUCP mailbox
controller hence fallback to it.
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Add compatible for the Qualcomm Shikra APCS block.
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Nord SoC, which is compatible with X1E80100 CPUCP, even though it supports
more IPC channels.
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Communication Controller
Document the Inter-Processor Communication Controller (IPCC) found in the
Qualcomm Eliza SoC. It is used to route interrupts across various
subsystems.
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar:
"Platform and core updates
PCC:
- Updates to transmission and interrupt handling, including dynamic
txdone configuration, ->last_tx_done() wiring, and SHMEM
initialization fixes. Reverted previous shared buffer patch
MediaTek
- Introduce mtk-vcp-mailbox driver and bindings for MT8196 VCP
- Expand mtk-cmdq for MT8196 with GCE virtualization, mminfra_offset,
and instruction generation data
Spreadtrum (SPRD)
- Add Mailbox Revision 2 support and UMS9230 bindings
- Fix unhandled interrupt masking and TX done delivery flags
Microchip
- Add pic64gx compatibility to MPFS
- Fix out-of-bounds access and smatch warnings in mchp-ipc-sbi
Core & Misc Platform Updates
- Prevent out-of-bounds access in fw_mbox_index_xlate()
- Add bindings for Qualcomm CPUCP (Kaanapali)
- Simplify mtk-cmdq and zynqmp-ipi with scoped OF child iterators
- Consolidate various minor fixes, dead code removal, and typo
corrections across Broadcom, NXP, Samsung, Xilinx, ARM, and core
headers"
* tag 'mailbox-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: (34 commits)
mailbox: sprd: mask interrupts that are not handled
mailbox: sprd: add support for mailbox revision 2
mailbox: sprd: clear delivery flag before handling TX done
dt-bindings: mailbox: sprd: add compatible for UMS9230
mailbox: bcm-ferxrm-mailbox: Use default primary handler
mailbox: Remove mailbox_client.h from controller drivers
mailbox: zynqmp-ipi: Simplify with scoped for each OF child loop
mailbox: mtk-cmdq: Simplify with scoped for each OF child loop
dt-bindings: mailbox: xlnx,zynqmp-ipi-mailbox: Document msg region requirement
mailbox: Improve RISCV_SBI_MPXY_MBOX guidance
mailbox: mchp-ipc-sbi: fix uninitialized symbol and other smatch warnings
mailbox: arm_mhuv3: fix typo in comment
mailbox: cix: fix typo in error message
mailbox: imx: Skip the suspend flag for i.MX7ULP
mailbox: exynos: drop unneeded runtime pointer (pclk)
mailbox: pcc: Remove spurious IRQF_ONESHOT usage
mailbox: mtk-cmdq: Add driver data to support for MT8196
mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
mailbox: mtk-cmdq: Add GCE hardware virtualization configuration
mailbox: mtk-cmdq: Add cmdq private data to cmdq_pkt for generating instruction
...
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Add a compatible string for the mailbox controller found in the UMS9230
SoC.
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Add description clarifying that for Versal IPI mailboxes, both host and
remote agents must have the "msg" register region defined for successful
message passing. Without both, only notification-based communication
works.
Signed-off-by: Harini T <harini.t@amd.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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pic64gx mailbox is compatible with mpfs mailbox, even if the mailbox
consumer is not - the underlying communication mechanism is the same.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Kaanapali, which is compatible with X1E80100, use fallback to indicate
this.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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The MTK VCP mailbox enables the SoC to communicate with the VCP by passing
messages through 64 32-bit wide registers. It has 32 interrupt vectors in
either direction for signalling purposes.
This adds a binding for Mediatek VCP mailbox.
Signed-off-by: Jjian Zhou <jjian.zhou@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document the Inter-Processor Communication Controller on the Qualcomm
Kaanapali and Glymur Platforms, which will be used to route interrupts
across various subsystems found on the SoC.
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251031-knp-ipcc-v3-1-62ffb4168dff@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Kaanapali, which is compatible with X1E80100, use fallback to indicate
this.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm
SM8750 SoCs. It is software compatible with X1E80100 CPUCP mailbox
controller hence fallback to it.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251211-sm8750-cpufreq-v1-1-394609e8d624@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Generally at most 1 blank line is the standard style for DT schema
files. Remove the few cases with more than 1 so that the yamllint check
for this can be enabled.
Acked-by: Lee Jones <lee@kernel.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> # remoteproc
Acked-by: Georgi Djakov <djakov@kernel.org>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Andi Shyti <andi.shyti@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Uwe Kleine-König <ukleinek@kernel.org> # for allwinner,sun4i-a10-pwm.yaml
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> # mtd
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Manivannan Sadhasivam <mani@kernel.org> # For PCI controller bindings
Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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yamllint has gained a new check which checks for inconsistent quoting
(mixed " and ' quotes within a file). Fix all the cases yamllint found
so we can enable the check (once the check is in a release). As single
quotes are (slightly) preferred, use them throughout the modified files
even if double quotes are mostly used.
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Acked-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://patch.msgid.link/20251015232015.846282-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Convert APM X-Gene slimpro-mbox binding to DT schema format. It's a
straight-forward conversion.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar:
- Qualcomm: add Glymur CPUCP mailbox binding
- Xilinx Zynq: misc cleanup
- MediaTek:
- add new GPUEB mailbox driver
- cmdq: remove pm_runtime calls from send_data
- gce: make clock-names optional
- misc:
- change mailbox-altera maintainer
- remove redundant 'fast_io' in regmap_config
- mhuv3: Remove no_free_ptr
* tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
mailbox: mtk-cmdq: Remove pm_runtime APIs from cmdq_mbox_send_data()
mailbox: add MediaTek GPUEB IPI mailbox
dt-bindings: mailbox: Add MT8196 GPUEB Mailbox
mailbox: zynqmp-ipi: Fix SGI cleanup on unbind
mailbox: zynqmp-ipi: Fix out-of-bounds access in mailbox cleanup loop
mailbox: zynqmp-ipi: Remove dev.parent check in zynqmp_ipi_free_mboxes
mailbox: zynqmp-ipi: Remove redundant mbox_controller_unregister() call
mailbox: remove unneeded 'fast_io' parameter in regmap_config
dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional
dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding
MAINTAINERS: Change mailbox-altera maintainer
mailbox: arm_mhuv3: Remove no_free_ptr() to maintain the original form of the pointer
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The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB",
acting as glue logic to control power and frequency of the Mali GPU.
This MCU runs special-purpose firmware for this use, and the main
application processor communicates with it through a mailbox.
Add a binding that describes this mailbox.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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The GCE Mailbox needs only one clock and the clock-names can be
used only by the driver (which, for instance, does not use it),
and this is true for all of the currently supported MediaTek SoCs.
Stop requiring to specify clock-names on all non-MT8195 GCEs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm
Glymur SoCs. It is software compatible with X1E80100 CPUCP mailbox
controller hence fallback to it.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull more RISC-V updates from Paul Walmsley:
- Support for the RISC-V-standardized RPMI interface.
RPMI is a platform management communication mechanism between OSes
running on application processors, and a remote platform management
processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip,
mailbox, and clk changes.
- Support for the RISC-V-standardized MPXY SBI extension.
MPXY is a RISC-V-specific standard implementing a shared memory
mailbox between S-mode operating systems (e.g., Linux) and M-mode
firmware (e.g., OpenSBI). It is part of this PR since one of its use
cases is to enable M-mode firmware to act as a single RPMI client for
all RPMI activity on a core (including S-mode RPMI activity).
Includes a mailbox driver.
- Some ACPI-related updates to enable the use of RPMI and MPXY.
- The addition of Linux-wide memcpy_{from,to}_le32() static inline
functions, for RPMI use.
- An ACPI Kconfig change to enable boot logos on any ACPI-using
architecture (including RISC-V)
- A RISC-V defconfig change to add GPIO keyboard and event device
support, for front panel shutdown or reboot buttons
* tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits)
clk: COMMON_CLK_RPMI should depend on RISCV
ACPI: support BGRT table on RISC-V
MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers
RISC-V: Enable GPIO keyboard and event device in RV64 defconfig
irqchip/riscv-rpmi-sysmsi: Add ACPI support
mailbox/riscv-sbi-mpxy: Add ACPI support
irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode()
ACPI: RISC-V: Add RPMI System MSI to GSI mapping
ACPI: RISC-V: Add support to update gsi range
ACPI: RISC-V: Create interrupt controller list in sorted order
ACPI: scan: Update honor list for RPMI System MSI
ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args()
ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop
irqchip: Add driver for the RPMI system MSI service group
dt-bindings: Add RPMI system MSI interrupt controller bindings
dt-bindings: Add RPMI system MSI message proxy bindings
clk: Add clock driver for the RISC-V RPMI clock service group
dt-bindings: clock: Add RPMI clock service controller bindings
dt-bindings: clock: Add RPMI clock service message proxy bindings
mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
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The GCE Mailbox needs only one clock and the clock-names can be
used only by the driver (which, for instance, does not use it),
and this is true for all of the currently supported MediaTek SoCs.
Stop requiring to specify clock-names on all non-MT8195 GCEs.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Add device tree bindings for the RISC-V SBI Message Proxy (MPXY)
extension as a mailbox controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-3-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
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Add device tree bindings for the common RISC-V Platform Management
Interface (RPMI) shared memory transport as a mailbox controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Link: https://lore.kernel.org/r/20250818040920.272664-2-apatel@ventanamicro.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
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Convert the Broadcom FlexRM Ring Manager binding to DT schema format.
It's a straightforward conversion.
Link: https://lore.kernel.org/r/20250812181415.66923-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Convert the Broadcom iProc PDC mailbox binding to DT schema format. It's
a straightforward conversion.
Link: https://lore.kernel.org/r/20250812181406.65390-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Convert the Marvell Armada 3700 rWTM mailbox binding to DT schema
format. It's a straightforward conversion.
Link: https://lore.kernel.org/r/20250812181357.63395-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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Convert the rockchip,rk3368-mailbox binding to DT schema format. Add
the missing 'clocks' and 'clock-names' properties. Document that it's
one interrupt per mailbox channel (and there are 4 channels).
Link: https://lore.kernel.org/r/20250812181348.62137-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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The mailbox hardware remains unchanged on M2 Pro/Max/Ultra SoCs so just
add its per-SoC compatible.
Reviewed-by: Neal Gompa <neal@gompa.dev>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Janne Grunau <j@jannau.net>
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Add bindings for ASC mailboxes as found on Apple A11 and T2 SoCs. These
mailboxes are used for coprocessors including Secure Enclave Processor
(SEP), the NVMe coprocessor and the system management controller.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250821-t8015-nvme-v3-1-14a4178adf68@gmail.com
Signed-off-by: Sven Peter <sven@kernel.org>
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