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8 daysMerge tag 'devicetree-for-7.4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - A bunch of improvements in dt-check-style. Fix various bindings based on these additional checks. - Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade, hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs, mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and ti,omap-ocp2scp to DT schema format - Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus, HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC - Various binding updates to fix schema warnings in .dts files - Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and regulator, and mailbox.txt - Remove the unused of_overlay_remove_all() function - Fixes for of_check_msi_parent() - Add "i2c-parent" tracking to fw_devlink * tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits) dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller dt-bindings: iommu: Describe MT8195 infra IRQs dt-bindings: clock: mediatek: Add MT8516 fallbacks dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY of: overlay: remove unused of_overlay_remove_all() dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema dt-bindings: bus: Add HiSilicon local bus dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC dt-bindings: vendor-prefixes: add Ambarella dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema of/irq: Stop the MSI walk at the first msi-parent of/irq: Fix device node refcount leak in of_check_msi_parent() dt-bindings: display: faraday,tve200: Use a level-high interrupt ...
10 daysMerge tag 'soc-dt-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "This is a rather large update of over 1000 non-merge commits touching devicetree files and bindings. A few notable SoC were added this time: - Apple M4 and A18 Pro are used in laptops, these follow the M3 model added in 7.2. - Google Laguna (aka Tensor G5) is used last year's Pixel phone generation. Unlike the earlier Tensor chips, this is not based on Samsung's Exynos family design but starts a new chip family. - Qualcomm's Hawi and Nord SoCs are two powerful chips using the custom Oryon cores. Product names and applications are so far not known, which means that Qualcomm is doing something right by upstreaming kernel support early. The ST stm32mp23xc/stm32mp25xc SoC support was previously removed because there were no users upstream, but they are back now that boards have shown up. Renesas RZ/G2M v3.0 (R8A774A3) is just a minor variation of the already supported SoC. In total, there are 81 new dts files for individual boards, and they are all over the place. Only one riscv based machine is added, the Milk-V Meles SBC using the T-Head th1520 chip. For 32-bit Arm, we have 13 new boards. About half are industrial embedded boards using NXP i.MX6/7 chips, the rest are older products: two Amazon tablets, two Motorola phones and two SoM boards. Everything else is 64-bit Arm: - many industrial embedded boards using NXP layerscape, NXP i.MX8/9, Qualcomm Hamoa, ST stm32mp2, Rockchip rk35xx, and Renesas RZ/G2 SoCs - Laptops and tablets using Apple M4, Qualcomm Snapdragon X2, Snapdragon X1 Elite and Allwinner A133 chips - Valve Steam Frame VR headset using Snapdragon 8 Gen 3 - Seven handheld game consoles using Qualcomm Dragonwing qcs8550 - Mobile phones using Google Tensor G5, Samsung Exynos 850, and various Qualcomm Snapdragon chips Aside from the new stuff, there is still a lot going on for existing socs and boards, including GPU hardware support on MediaTek MT8173 based laptops. Most patches actually add features this time, as the compile-time diagnostic changes are slowing down" * tag 'soc-dt-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (1022 commits) arm64: dts: rockchip: Add Radxa E54C dt-bindings: arm: rockchip: Add Radxa E54C arm64: dts: rockchip: remove FRL GPIO for 100ASK DshanPi A1 arm64: dts: rockchip: fix M.2 E-key reset pinctrl on rk3588 rock-5-itx arm64: dts: rockchip: add pcie30phy data-lanes on rk3588 coolpi-cm5-evb arm64: dts: rockchip: Add the fan tachometers to Kobol Helios64 arm64: dts: rockchip: enable NPU on Radxa E52C arm64: dts: rockchip: fix adc button voltage on Radxa E52C riscv: dts: sophgo: sg2002-milkv-duo256m: drop reserved memory node riscv: dts: sophgo: cv1800b-milkv-duo: drop reserved memory node arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes arm64: dts: nuvoton: npcm845-evb: Fix DTS coding style arm64: dts: nuvoton: npcm845: Add peripheral nodes arm64: dts: nuvoton: npcm845: Split APB address ranges riscv: dts: sophgo: cv180x: Fix internal ephy node name riscv: dts: sophgo: add Milk-V Duo 256M ethernet support overlay riscv: dts: sophgo: Limit SG2042 SPI NOR to 12.5 MHz riscv: dts: sophgo: Enable SPI NOR on SRD3-10 riscv: dts: spacemit: set ETH MAC from eeprom for OrangePi arm64: dts: allwinner: sun50i-h616: Add video engine ...
2026-10-16Merge tag 'spacemit-dt-for-7.4-1' of ↵Alexandre Belloni
https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux into soc/dt RISC-V SpacemiT DT changes for 7.4 For K3 SoC - Correct CLINT and ACLINT - Add USB nodes info - Add cpu scaling - Add rfkill node - Add i2s info - Fix IMSIC - Enable thermal and fan control (CTF230) For K1 SoC - Set mac address from eeprom - Enable onboard eeprom MISC Changes: - MAINTAINERS updates * tag 'spacemit-dt-for-7.4-1' of https://git.kernel.org/pub/scm/linux/kernel/git/spacemit/linux: (27 commits) riscv: dts: spacemit: set ETH MAC from eeprom for OrangePi riscv: dts: spacemit: k3: Replace incorrect CLINT node with ACLINT nodes irqchip/aclint-sswi: Add support for SpacemiT K3 dt-bindings: timer: sifive,clint: Remove spacemit,k3-clint dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3 dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3 dt-bindings: timer: thead,c900-aclint-mtimer: Add SpacemiT K3 riscv: dts: spacemit: k3-com260-ifx: Add rfkill nodes riscv: dts: spacemit: k3-com260-ifx: Add USB nodes riscv: dts: spacemit: k3-com260: keep dldo4 enabled riscv: dts: spacemit: k3: add rfkill node for WLAN on the K3 Pico-ITX board riscv: dts: spacemit: k3: add rfkill node for Bluetooth on Pico-ITX board riscv: dts: spacemit: k3: add USB3 B and C controllers for Pico-ITX board riscv: dts: spacemit: k3: move USB3 phy to board level riscv: dts: spacemit: set console baud rate on OrangePi RV2 riscv: dts: spacemit: orangepi-r2s: Add cpu scaling for K1 SoC riscv: dts: spacemit: orangepi-rv2: Add cpu scaling for K1 SoC riscv: dts: spacemit: k1-musepi-pro: add cpu scaling MAINTAINERS: add entry for SpacemiT reset controller driver riscv: dts: spacemit: k3: add i2s0-i2s5 nodes ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
2026-10-15dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDCSreeshankar K
Document the PDC block on the SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20261015051926.13752-5-sreeshankar0910@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-10-15dt-bindings: interrupt-controller: amazon,al-fic: Add mask selectionEliav Farber
The block this driver calls a FIC is the generic Annapurna Labs interrupt controller. It is built from groups of up to 32 triggers each; the number of groups differs from one controller to another, and each group has its own 0x40 register block. A node in this binding describes one group, not a whole controller. reg points at that group's 0x40 block, and the 32 hwirqs of the domain are that group's triggers. A controller with several groups appears as several nodes, and controllers cascade when a tree needs more triggers than one controller has. A group has one cause register and three mask registers, which decide which output a set cause bit drives: 0x10 info mask gates the info output 0x2c error mask gates the error output 0x34 fatal mask gates the fatal output The three outputs are aggregated into three separate interrupt trees (info, error, fatal); mapping one event to more than one severity is forbidden by the interrupt methodology, so a group belongs to exactly one tree. Which output a group drives is fixed when the SoC is wired and is not discoverable from any register, so it must be described in the devicetree. The error and fatal outputs, and their mask registers, exist only on controller revisions that implement them; earlier revisions provide the info output only. A controller reports its revision in the group control register (bits 29-28), so the revision itself does not need to appear in the devicetree and no per-revision compatible string is needed. Describe which output a group drives with a new optional property, amazon,al-fic-mask (info, error or fatal; default info). Signed-off-by: Eliav Farber <farbere@amazon.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Radu Rendec <radu@rendec.net> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20261011050449.41903-7-farbere@amazon.com
2026-10-15dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraintsLorenzo Pieralisi
An IRS is architecturally allowed to be stand-alone (ie with no direct CPU connection). Relax "cpus" and "arm,iaffids" properties constraints allowing a standalone IRS configuration. Fixes: 7d7299bd07c6 ("dt-bindings: interrupt-controller: Add Arm GICv5") Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://patch.msgid.link/20261015-gicv5-irs-no-cpus-v1-1-d4b337b7f000@kernel.org
2026-10-15dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSRAnirudha Sarangi
Add a device tree binding schema for the Xilinx Versal NET SMMU CSR (Control and Status Register) interrupt controller. The SMMU CSR block acts as a vendor-specific interrupt controller in front of the ARM SMMUv3, providing registers to enable and clear standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ. Interrupts must be acknowledged in this block before being forwarded to the parent interrupt controller (e.g. GIC). Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com> Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com> Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260928-smmu-changes-v2-v4-1-3c79a14cd806@amd.com
2026-10-02dt-bindings: interrupt-controller: thead,c900-aclint-sswi: Add SpacemiT K3Junhui Liu
Add support for the SpacemiT K3 ACLINT SSWI, which provides inter-processor interrupts in Supervisor mode without calling into Machine-mode firmware. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260918-k3-aclint-v3-3-cf4fd4050e14@pigmoral.tech Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-10-02dt-bindings: interrupt-controller: thead,c900-aclint-mswi: Add SpacemiT K3Junhui Liu
Add support for the SpacemiT K3 ACLINT MSWI, which provides per-hart software interrupts for inter-processor communication in Machine mode. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Yixun Lan <dlan@kernel.org> Link: https://patch.msgid.link/20260918-k3-aclint-v3-2-cf4fd4050e14@pigmoral.tech Signed-off-by: Yixun Lan <dlan@kernel.org>
2026-09-25dt-bindings: interrupt-controller: apple,aic2: Add t8140 compatibleYureka Lilian
The Apple t8140 (A18 Pro) SoC uses an AIC3 as interrupt controller, same as the M3-M4 SoCs. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev> Reviewed-by: Sven Peter <sven@kernel.org> Link: https://patch.msgid.link/20260924-apple-a18-pro-initial-devicetrees-v3-4-94f7ea52cc64@cyberchaos.dev Signed-off-by: Sven Peter <sven@kernel.org>
2026-09-17dt-bindings: interrupt-controller: chrp,open-pic: Fix dangling referenceGeert Uytterhoeven
The target of "[1]" was lost during the conversion to json-schema. Replace it by an inline reference. Fixes: a241f1a1b338b714 ("dt-bindings: interrupt-controller: Convert chrp,open-pic to DT schema") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/86dd3544f7286fc117dc7ad0f6d799761283ec54.1788426169.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-09-17dt-bindings: interrupt-controller: chrp,open-pic: Typo s/pci/pic/Geert Uytterhoeven
The device_type for an OpenPIC node is "open-pic", not "open-pci". Fixes: a241f1a1b338b714 ("dt-bindings: interrupt-controller: Convert chrp,open-pic to DT schema") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/f2cc11922b3e5dd73997ef8c673137951d3fe715.1788426169.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-09-04dt-bindings: interrupt-controller: qcom,pdc: Add Kuno compatible stringHardeep Sharma
Document the Power Domain Controller found on the Qualcomm Kuno SoC. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Hardeep Sharma <hardeep.sharma@oss.qualcomm.com> Link: https://patch.msgid.link/20260827-kuno-soc-support-v5-12-6d47636a8f09@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-09-04dt-bindings: interrupt-controller: qcom,pdc: Document Purwa PDCMaulik Shah
X1P42100 (Purwa) shares the X1E80100 (Hamoa) PDC device, but the hardware register bug addressed in commit e9a48ea4d90b ("irqchip/qcom-pdc: Workaround hardware register bug on X1E80100") is already fixed in X1P42100 silicon. X1E80100 compatible forces the software workaround. Add PDC compatible for purwa as "qcom,x1p42100-pdc" to remove the workaround from Purwa. Signed-off-by: Maulik Shah <maulik.shah@oss.qualcomm.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260806-purwa-pdc-v4-1-62467f4b4ddc@oss.qualcomm.com
2026-08-31dt-bindings: interrupt-controller: apple,aic2: Add apple,t8132 compatibleYureka Lilian
The Apple t8132 (M4) SoC uses an AIC3 as interrupt controller, same as the M3 predecessor. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Yureka Lilian <yureka@cyberchaos.dev> Reviewed-by: Linus Walleij <linusw@kernel.org> Link: https://patch.msgid.link/20260811-apple-m4-initial-devicetrees-v3-2-6bf32d45ad0b@cyberchaos.dev Signed-off-by: Sven Peter <sven@kernel.org>
2026-08-19Merge tag 'devicetree-for-7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: - Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style * tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits) dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible dtc: dt-check-style: Simplify setting depth of DtsLine dtc: dt-check-style: Add missing /dts-v1/ to few test cases dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema media: dt-bindings: ti,da850-vpif: Convert to dt-schema dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer dt-bindings: arm: omap: Convert L4 interconnect to DT schema dt-bindings: power: Convert TI SmartReflex to DT schema of: reserved_mem: Introduce devres-managed initialization function dt-bindings: interrupt-controller: Add StarFive JHB100 plic dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller dt-bindings: Correct white-space style dt-bindings: fix typos and brackets docs: dt: submitting-patches: Mention expectation about dt-check-style docs: dt: maintainer: Add Devicetree and OF maintainer profile document docs: dt: writing-schema: Extend expectations about example part of binding dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU of: base: Handle optional argument in of_parse_phandle_with_args_map() dt-bindings: update Sudeep Holla's email address ...
2026-08-18Merge tag 'soc-drivers-7.3' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The SoC driver changes once more consist of many small fixes and cleanups, that are to a large part the result of automated testing. On platform specific drivers, this includes SoC specific code for xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip, renesas, ixp4xx. In firmware drivers, we see a similar picture for SCMI and qcomtee. Aside from these, we see actual new hardware support in a few areas: - The Apple platform gets a new driver for low power states - Updates to Qualcomm platform drivers add several new hardware specific features and additional SoCs. - Amlogic SoC support for A1 and T7 is added - The Mediatek MMSYS driver is refactored as a cleanup" * tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits) soc: qcom: make QCOM_PDR_MSG selectable soc: qcom: ubwc: Fix missing include soc: qcom: ubwc: Fix link error when QCOM_SMEM=n media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850 firmware: xilinx: Clear firmware notifiers across kexec transitions firmware: xilinx: Release all peripheral devices from firmware firmware: xilinx: Add support to clear EL3 PM state firmware: xilinx: Propagate actual error from feature check firmware: xilinx: Use TF-A feature check for TF-A-specific APIs bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state ...
2026-08-18Merge tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are two new mystery SoCs with very little public information about them so far, Qualcomm's Cortex-A78C based "Shikra" and Altera's Cortex-A720 based Agilex72 SOCFPGA. We have also gained support for a couple of SoCs from the 2023/2024 timeframe that have been in the making for a while: - The Apple platform gains support for M3 Pro, Max and Ultra SoC, following the basic M3 support from 7.2. - Samsung Exynos 1580 is a high-end mobile phone SoC from 2024 - Canaan K230 is a RISC-V based 64-bit AI SoC, based on the earlier K210 chip - Sophgo SG2000 is a mixed Arm/RISC-V chip that was already supported using the Arm core but is now also added for RISC-V along with several other variants of the cv18xx series In terms of newly added machines we have reference platforms for all the chips above, plus - Only four 32-bit Arm boards: two older phones and two older industrial/embedded boards; using Allwinner, Qualcomm and Rockchip SoCs - Three laptops und three phones using Qualcomm SoCs - Ten 64-bit Rockchips based single-board computers, along with one NAS box and a game console. - Seven industrial/embedded boards and modules using NXP i.MX8/9 SoCs. - A Lenovo desktop box based on NVIDIA Jetson Xavier NX - A few more single-board computers based on Allwinnner A133, Spacemit K1 and TI AM62. As usual, there is a constant stream of minor cleanups and fixes towards addressing the 'dt-check-style --mode strict' warnings, and everyone is expected to address those warnings for new submissions now" * tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (864 commits) Revert "riscv: dts: spacemit: k3: add i2s0-i2s5 nodes" Documentation/process: maintainer-soc: Mention expectation about dt-check-style ARM: dts: helios4: add SATA regulator supplies ARM: dts: helios4: add vcc-supply to GPIO expander ARM: dts: helios4: add vcc-supply to EEPROM arm64: dts: turris-mox: fix usb3 phys arm64: dts: ti: Correct white-space style arm64: dts: ti: k3-am64: Fix MDIO clock reference for ICSSG0 node arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies ...
2026-08-14dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON ↵Rob Herring (Arm)
pointer The $ref "arm,gic.yaml#/properties/#interrupt-cells" doesn't work when used with another json-schema implementation (rust). The issue is it not a valid URI due to the 2nd "#" character in the JSON pointer. Though a "#" is supposed to be valid within a JSON pointer. A possible solution is to encode the "#" as "%23" instead, but the dtschema tools don't handle that. Just avoid all these issues as the $ref only resolves to a "const: 3" schema and specify it directly. Link: https://patch.msgid.link/20260813145453.1919998-1-robh@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-08-11dt-bindings: interrupt-controller: Add StarFive JHB100 plicLey Foon Tan
Add compatible string for StarFive JHB100 plic. Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Link: https://patch.msgid.link/20260806122553.182449-3-changhuang.liang@starfivetech.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-08-10Merge tag 'apple-soc-dt-7.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt Apple SoC DTS changes for 7.3 - Initial M3 Pro, Max and Ultra device trees, which are responsible for the majority of the diffstat. These include CPU cores, interrupt controller, power state, watchdog, serial pin/gpio controller, i2c and the boot framebuffer. They are now on par with the base M3 device trees. - HWMON sensors for M1/M2 - "pmgr-misc" nodes for M1/2 Pro/Max/Ultra which saves about 1W of power on these machines. The corresponding driver and dt-binding are part of the Apple SoC driver changes tag for this cycle. Signed-off-by: Sven Peter <sven@kernel.org> * tag 'apple-soc-dt-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: (22 commits) arm64: dts: apple: Initial T6030 (M3 Pro) device trees arm64: dts: apple: Initial T603[124] (M3 Max and Ultra) device trees dt-bindings: pwm: apple,s5l-fpwm: Add t6030 and t6031 compatibles dt-bindings: i2c: apple,i2c: Add t6030 and t6031 compatibles dt-bindings: power: apple,pmgr-pwrstate: Add t6030 and t6031 compatibles dt-bindings: arm: apple: apple,pmgr: Add t6030 and t6031 compatibles dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatible dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells condition dt-bindings: arm: apple: Add M3 Pro/Max/Ultra devices (T603x) arm64: dts: apple: t60xx: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t8112: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t8103: jxxx: Add device-specific SMC hwmon sensors arm64: dts: apple: t602x: Add common SMC hwmon sensors arm64: dts: apple: t600x: Add common SMC hwmon sensors arm64: dts: apple: t8112: Add common SMC hwmon sensors arm64: dts: apple: t8103: Add common SMC hwmon sensors arm64: dts: apple: Add common SMC hwmon infrastructure arm64: dts: apple: t602x: Add SMC hwmon node arm64: dts: apple: t600x: Add SMC hwmon node arm64: dts: apple: t8103: Add SMC hwmon node ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-08-07dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controllerJerome Brunet
The A733 NMI controller is compatible with the A523 one. Add an A733-specific compatible string, with the A523 as fallback. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260731-allwinner-a733-nmi-support-v1-1-61e4a0825b20@baylibre.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-08-03dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt ↵Paul Louvel
type encoding The QUICC Engine port interrupt controller can be configured to generate an interrupt on either a high-to-low transition or any change in the signal state on the related GPIOs. Update the #interrupt-cells property to 2 so consumers can encode interrupt level information. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com> Reviewed-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> Link: https://lore.kernel.org/r/20260708-qe-pic-gpios-v2-2-1972044cfbd1@bootlin.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>
2026-08-01dt-bindings: interrupt-controller: apple,aic2: Add apple,t6031-aic3 compatibleJanne Grunau
The Apple M3 Max and Ultra SoCs use AICv3 as interrupt controller. It is compatible to the base M3 AICv3. Add "apple,t6031-aic3" as compatible and add it to the list for 4 #interrupt-cells used for multi-die SoCs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Sven Peter <sven@kernel.org>
2026-08-01dt-bindings: interrupt-controller: apple,aic2: Invert #interrupt-cells conditionJanne Grunau
The condition for 3 or 4 #interrupt-cells list compatibles for the 3 cells variant (not used in SoCs consisting out of multiple dies). This includes the AICv3 base compatible "apple,t8122-aic3". This will match compatible = "apple,t6031-aic3", "apple,t8122-aic3"; shared for M3 Max and Ultra based devices which require the additional interrupt cell for the die number. Instead list the compatibles used for multi-die SoCs explicitly and use 4 #interrupt-cells for them. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Sven Peter <sven@kernel.org>
2026-07-24Merge tag 'riscv-dt-for-v7.3-early-k230' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V devicetrees for v7.3 - early k230 material Canaan: Support for the k230 SoC that was too late for the 7.2 window. Consists of some bindings not taken by the various subsystem maintainers, the original dts patches from Yangyu back in 2024 and the more recent clock, reset and pinctrl additions from various contributors. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v7.3-early-k230' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: canaan: Add clock definition for K230 riscv: dts: canaan: add reset controller for K230 riscv: dts: canaan: k230: Add "b" ISA extension riscv: dts: canaan: Add k230's pinctrl node riscv: dts: canaan: Correct the formatting issues about k230 dts riscv: dts: add initial canmv-k230 and k230-evb dts dt-bindings: interrupt-controller: Add Canaan K230 PLIC dt-bindings: timer: Add Canaan K230 CLINT dt-bindings: add Canaan K230 boards compatible strings Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2026-06-29dt-bindings: interrupt-controller: realtek,rtl-intc: Allow 2 interrupt cellsMarkus Stockhausen
The Realtek Otto SoC interrupt controller supports hardware interrupt routing to multiple parent CPU interrupt lines. To utilize this multi-domain support, peripheral devices need a way to explicitly specify their desired parent interrupt line in the device tree. Update the "#interrupt-cells" property to accept either 1 or 2 cells. 1 cell: Specifies the hardware interrupt index, implicitly routing it to the first available parent (maintaining backward compatibility). 2 cells: The first cell specifies the hardware interrupt index and the second cell specifies the targeted parent interrupt index. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260605211646.2101652-2-markus.stockhausen@gmx.de
2026-06-17Merge tag 'devicetree-for-7.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add support for handling multiple cells in "iommu-map" entries - Support only 1 entry in /reserved-memory "reg" entries. Support for more than 1 entry has been broken - Fix a UAF on alloc_reserved_mem_array() failure - Make "ibm,phandle" handling logic specific to PPC - Use memcpy() instead of strcpy() for known length strings - Ensure __of_find_n_match_cpu_property() handles malformed "reg" entries - Add various checks that expected strings are strings before accessing them - Drop redundant memset() when unflattening DT DT bindings: - Add a DTS style checker. Currently hooked up to dt_binding_check to check examples - Convert st,nomadik platform, ti,omap-dmm, and ti,irq-crossbar bindings to DT schema - Add Apple System Management Controller hwmon, Qualcomm Hamoa Embedded Controller, Qualcomm IPQ6018 PWM controller, fsl,mc1323, Samsung SOFEF01-M DDIC panel, Freescale i.MX53 Television Encoder, Samsung S2M series PMIC extcon, and MT6365 PMIC AuxADC schemas - Extend bindings for QCom Maili and Nord PDC, QCom Hali fastrpc, qcom,eliza-imem, qcom,oryon-1-5 CPU, and MT6365 Keys - Consolidate "sram" property definitions - Fix constraints on "nvmem" properties which only contain phandles and no arg cells - Another pass of fixing "phandle-array" constraints - Add Gira vendor prefix" * tag 'devicetree-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (50 commits) dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible string dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schema dt-bindings: vendor-prefixes: add Gira dt-bindings: embedded-controller: Add Qualcomm reference device EC description dt-bindings: pwm: add IPQ6018 binding dt-bindings: hwmon: Add Apple System Management Controller hwmon schema docs: dt: writing-schema: Clarify what is required in a schema of: Respect #{iommu,msi}-cells in maps of: Factor arguments passed to of_map_id() into a struct of: Add convenience wrappers for of_map_id() of: reserved_mem: zero total_reserved_mem_cnt if no valid /reserved-memory entry of: reserved_mem: handle NULL name in of_reserved_mem_lookup() dt-bindings: cache: l2c2x0: Add missing power-domains dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in example dt-bindings: nvmem: consumer: Make 'nvmem' an array of one-item entries drivers/of/overlay: Use memcpy() to copy known length strings dt-bindings: add self-test fixtures for style checker dt-bindings: wire style checker into dt_binding_check scripts/jobserver-exec: propagate child exit status dt-bindings: add DTS style checker ...
2026-06-17Merge tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC devicetree updates from Arnd Bergmann: "There are fewer devicetree updates this time that the last few ones, with five SoC types getting added: - Qualcomm Dragonwing IPQ9650 is a new wireless networking SoC using four Cortex-A55 and one Cortex-A78 core, which is a significant upgrade from older generations - ZTE zx297520v3 is an older low-end wireless SoC using a single Cortex-A53 core, which so far can only run 32-bit kernels. This brings back the ZX family of chips that was removed in 2021 after support for the original zx296702 and zx296718 chips was never completed. - Renesas R-Car M3Le (R8A779MD) is a variant of the R-Car M3-N (R8A77965) automotive SoC. - Apple t8122 (M3) is the 2023 generation of their laptop SoCs, which has now been reverse-engineered to the point of having initial kernel support for five laptop models. - ASPEED AST27xx is their first baseboard managment controller using a 64-bit core, the Cortex-A35, following earlier generations using ARMv5/v6/v7 CPUs. These all come with one or more initial boards, and in total there are 39 new boards getting added across SoC families, including: - Two NAS boxes using the old Cortina Systems Gemini SoC based on an ARMv4 FA526 CPU core - 18 industrial embedded boards using NXP i.MX6/8/9 and LX2160A SoCs from Variscite, Toradex and SolidRun, plus a number of overlays for combinations with additional boards - One new carrier board and SoM using TI K3 AM62x, in addition to new overlays for older SoMs - Two new boards using Spacemit K3 (no relation with TI) RISC-V SoCs. - Three phones from Google, Nothing and Motorola, all using Qualcomm Snapdragon SoCs - AST26xx BMC support for two server boards While there is still a significant number of patches improving hardware support for the existing boards across vendors (NXP, Qualcomm, Renesas, Rockchips, Mediatek, ...), a much smaller number of cleanups and warning fixes have made it in this time" * tag 'soc-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (665 commits) arm64: dts: aspeed: Fix duplicate pinctrl labels and address scheme arm64: dts: bst: enable eMMC controller in C1200 dt-bindings: display/lvds-codec: add ti,sn65lvds93 arm64: dts: allwinner: a523: Add missing GPIO interrupt arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap arm64: dts: aspeed: Add initial AST27xx SoC device tree arm64: Kconfig: Add ASPEED SoC family Kconfig support dt-bindings: arm: aspeed: Add AST2700 board compatible arm64: dts: allwinner: a523: add gpadc node arm64: dts: allwinner: Add EL2 virtual timer interrupt ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node dt-bindings: media: sun6i-a31-isp: Add optional interconnect properties dt-bindings: media: sun6i-a31-csi: Add optional interconnect properties arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays arm64: dts: imx93-var-som-symphony: enable ADC arm64: dts: imx93-var-som-symphony: enable TPM3 PWM arm64: dts: imx93-var-som-symphony: keep RGB_SEL low arm64: dts: imx93-var-som-symphony: enable UART7 arm64: dts: imx93-var-som-symphony: add TPM support arm64: dts: imx91-var-som-symphony: fix RGB_SEL handling ...
2026-06-16dt-bindings: interrupt-controller: qcom,pdc: Add Maili compatible stringYijie Yang
Register qcom,maili-pdc as a supported compatible string for the Qualcomm PDC interrupt controller binding. Signed-off-by: Yijie Yang <yijie.yang@oss.qualcomm.com> Link: https://patch.msgid.link/20260615-maili-pdc-v1-1-add21e8eec3e@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-15dt-bindings: interrupt-controller: ti,irq-crossbar: Convert to DT schemaBhargav Joshi
Convert TI irq-crossbar binding from text format to DT schema. As part of conversion following changes are made: - Add '#interrupt-cells' as a required property which was missing in text binding - As irq-crossbar is interrupt-controller. Move binding from bindings/arm/omap to bindings/interrupt-controller Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Link: https://patch.msgid.link/20260612-crossbar-v3-1-266747bc2e86@gmail.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-14dt-bindings: interrupt-controller: Add Canaan K230 PLICYangyu Chen
Add compatible string for Canaan K230 PLIC. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-06-10dt-bindings: interrupt-controller: renesas,r9a09g077-icu: Fix reg size in ↵Geert Uytterhoeven
example According to Figure 5.1 ("Unified memory map"), the safety register block is 64 KiB large, just like the non-safety register block. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/364ff570c8a1845fab24bd89557f06c9e406f8de.1781105007.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-06-02dt-bindings: soc: sophgo: add sg2000 plic and clint documentationJoshua Milas
Document the compatible strings for the sg2000 interrupt controller and timer. Signed-off-by: Joshua Milas <josh.milas@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260530173347.33533-4-josh.milas@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
2026-05-13dt-bindings: interrupt-controller: Document PDC for Qualcomm Nord SoCShawn Guo
Document Power Domain Controller on Qualcomm Nord SoC. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260504080703.825328-1-shengchao.guo@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-05-11dt-bindings: interrupt-controller: econet: Add CPU interrupt mappingCaleb James DeLisle
In MIPS VEIC mode (Vectored External Interrupt Controller), the hardware stops directly dispatching CPU interrupts such as IPIs or CPU performance counters, and instead it communicates them to the external interrupt controller (the hardware described here) which prioritizes, renumbers, and integrates them with its own hardware interrupt pins. Interrupts from the external controller are then dispatched through a different method via a dispatch table. In effect, the external controller subsumes the CPU controller and becomes the root. 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136 Since there are interrupts which ought to be controlled by the CPU controller driver - particularly the IPI interrupts - we create a reverse mapping where those interrupts may be sent back to the CPU intc when they are received. This maintains the fiction that there is still a hierarchy, and keeps the DT the same no matter whether the processor is in VEIC mode or not. The econet,cpu-interrupt-map is optional and if omitted, it's assumed that no interrupts need to be mapped. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr
2026-05-11dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCsXianwei Zhao
Update dt-binding document for GPIO interrupt controller of Amlogic A9 SoCs. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com
2026-04-30dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 ↵Changhuang Liang
for jhb100 The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com
2026-04-30dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0Ryan Chen
Introduce a new binding describing the AST2700 interrupt controller architecture implemented in the A2 production silicon. The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2) prior to mass production. The interrupt architecture was substantially reworked after the A0 revision for A1, and the A1 design is retained unchanged in the A2 production silicon. The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic") was written against the pre-production A0 design. That binding does not accurately describe the interrupt hierarchy and routing model present in A1/A2, where interrupts can be routed to multiple processor-local interrupt controllers (Primary Service Processor (PSP) GIC, Secondary Service Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU APLIC) depending on the execution context. Remove the binding for the pre-production A0 design in favour of the binding for the A2 production design. There is no significant user impact from the removal as there are no existing devicetrees in any of Linux, u-boot or Zephyr that make use of the A0 binding. Hardware connectivity between interrupt controllers is expressed using the aspeed,interrupt-ranges property. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260407-irqchip-v5-1-c0b0a300a057@aspeedtech.com
2026-04-17Merge tag 'devicetree-for-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Cleanup of the reserved memory code to keep CMA specifics in CMA code - Add and convert several users to new of_machine_get_match() helper - Validate nul termination in string properties - Update dtc to upstream v1.7.2-69-g53373d135579 - Limit matching reserved memory devices to /reserved-memory nodes - Fix some UAF in unittests - Remove Baikal SoC bus driver - Fix false DT_SPLIT_BINDING_PATCH checkpatch warning - Allow fw_devlink device-tree on x86 - Fix kerneldoc return description for of_property_count_elems_of_size() DT bindings: - Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc, qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem, qcom,hawi-pdc, and lg,sw49410 bindings - Convert arm,vexpress-scc to DT schema - Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores. - Move some dual-link display panels to the dual-link schema - Drop mux controller node name constraints - Remove Baikal SoC bus bindings - Fix a false warning in the thermal trip node binding" * tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits) dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes of: unittest: fix use-after-free in testdrv_probe() of: unittest: fix use-after-free in of_unittest_changeset() dt-bindings: qcom,pdc: document the Hawi Power Domain Controller dt-bindings: ARM: arm,vexpress-scc: convert to DT schema drivers/of: fdt: validate flat DT string properties before string use drivers/of: fdt: validate stdout-path properties before parsing them dt-bindings: sram: Document qcom,hawi-imem compatible dt-bindings: sram: Allow multiple-word prefixes to sram subnode dt-bindings: sram: Document qcom,milos-imem scripts/dtc: Update to upstream version v1.7.2-69-g53373d135579 of: property: Allow fw_devlink device-tree on x86 dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles dt-bindings: display: lt8912b: Drop redundant endpoint properties dt-bindings: opp-v2: Fix example 3 CPU reg value dt-bindings: connector: add pd-disable dependency ...
2026-04-16Merge tag 'soc-drivers-7.1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ...
2026-04-15dt-bindings: qcom,pdc: document the Hawi Power Domain ControllerMukesh Ojha
Document the Power Domain Controller on the Qualcomm Hawi SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260401125004.592925-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-04-04Merge tag 'tegra-for-7.1-dt-bindings' of ↵Krzysztof Kozlowski
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers dt-bindings: Changes for v7.1-rc1 This contains a few conversions to DT schema along with various additions and fixes to reduce the amount of validation warnings. Included are also a new binding for the PCIe controller found on Tegra264 as well as compatible strings for the Jetson AGX Thor Developer Kit. * tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit dt-bindings: display: tegra: Document Tegra20 HDMI port dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings dt-bindings: memory: tegra210: Mark EMC as cooling device dt-bindings: memory: Add Tegra210 memory controller bindings dt-bindings: phy: tegra: Document Tegra210 USB PHY dt-bindings: arm: tegra: Add missing compatible strings dt-bindings: interrupt-controller: tegra: Fix reg entries dt-bindings: clock: tegra124-dfll: Convert to json-schema dt-bindings: phy: tegra-xusb: Document Type C support dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2026-03-27dt-bindings: interrupt-controller: tegra: Fix reg entriesThierry Reding
Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30 which supports only 5 entries. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-03-26dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 supportCiprian Marian Costea
Add compatible string for the interrupt steering controller used in NXP S32N79 SoC. The S32N79 SoC differs from the i.MX version by not implementing the CHANCTRL register, but otherwise maintains the same programming model and register layout. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
2026-03-26dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3L SoCBiju Das
Document RZ/G3L (R9A08G046) IRQC. The IRQC block on the RZ/G3L SoC is nearly identical to that found on the RZ/G3S SoC, with the following differences: it supports more external interrupts and GPT error interrupts, and adds registers for GPT/MTU interrupt selection and shared interrupt selection between external interrupt and TINT. A new compatible string "renesas,r9a08g046-irqc" is therefore introduced for the RZ/G3L SoC. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-3-biju.das.jz@bp.renesas.com
2026-03-26dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Use pattern for ↵Biju Das
interrupt-names Simplify the bindings by using pattern property for interrupt-names. It also allows to change the ordering of interrupts. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260325192451.172562-2-biju.das.jz@bp.renesas.com
2026-03-26dt-bindings: interrupt-controller: Add LS7A PCH LPCIcenowy Zheng
Loongson 7A series PCH contains an LPC controller with an interrupt controller. Add the device tree binding for the interrupt controller. Signed-off-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260321092032.3502701-4-zhengxingda@iscas.ac.cn
2026-03-12dt-bindings: interrupt-controller: arm,gic-v3: Fix EPPI rangeGeert Uytterhoeven
According to the "Arm Generic Interrupt Controller (GIC) Architecture Specification, v3 and v4", revision H.b[1], there can be only 64 Extended PPI interrupts. [1] https://developer.arm.com/documentation/ihi0069/hb/ Fixes: 4b049063e0bcbfd3 ("dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Brain-farted-by: Marc Zyngier <maz@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://patch.msgid.link/3e49a63c6b2b6ee48e3737adee87781f9c136c5f.1772792753.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2026-03-11dt-bindings: interrupt-controller: apple,aic2: Add AICv3Janne Grunau
AIC version 3 as found on the Apple M3 (t8122) is very similar to AICv2 in its base functionality. It can use the same device tree bindings as AICv2 so add it to the AICv2 bindings. This interrupt controller is used on all Apple SoCs starting with M3 up to at least M5. The only apparent difference is the increased IRQ config offset. Apple's device tree codes this new offset as property of the "aic" node but the value stayed constant for all SoCs with "aic,3". Since the SoC specific compatible "apple,t8122-aic3" will be only used in the driver this offset can remain a driver implementation detail. Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260223-irq-apple-aic3-v3-1-2b7328076b8d@jannau.net