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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Here's the clk changes for the merge window which is dominated in the
diffstat by Qualcomm churning out new SoCs that need clk drivers.
Looking beyond the sheer amount of lines of mostly data there we have
a clk nexus DT binding change in the core clk framework and a driver
core patch to add a subsys driver macro.
The clock nexus support is useful for devices that map clks internally
or for connectors on a board that route clock signals to another
board. I suspect the use of this will expand in the future, so we have
unit tests to make sure it doesn't break.
The driver core change adds subsys_driver() and
subsys_platform_driver() so we can register early drivers without
open-coding that all (module_platform_driver() is at device initcall
level so it isn't be used).
Beyond the core framework bits we have lots of changes all over the
tree to initialize 'struct clk_init_data'. The potential risk here is
that someone forgets to initialize all the members of that structure
and either the clk flags cause weird behavior later on or the parents
are pointing at junk and the clk is orphaned forever. The patches just
initialize the thing with zeroes to be safe. Longer term we should
probably move this struct out of 'struct clk_hw' and pass it during
clk registration time. That's a much bigger change and would require
restructuring entire drivers that rely on the pointer being there.
Finally, we have the usual fixes like calculation updates for
dividers, handling error paths during clk registration, or fixing clk
data now that drivers are using them. Those patches are dwarfed by the
amount of new SoC support and only affect those SoCs and the consumers
of those clks. Overall I'm more concerned the clk_init_data patches
are going to expose some latent bugs that we didn't notice before
because something was relying on clks being orphaned and now they're
not.
Core:
- subsys_driver() / subsys_platform_driver() macros
- Clock nexus DT binding support (with KUnit tests)
- Spread-spectrum configuration validation
- Fully initialize struct clk_init_data across many drivers
New Drivers:
- Anlogic DR1V90 CRU
- ZTE zx297520v3 top, matrix, and LSP clocks
- Samsung Exynos5515 and ACPM driver extended to Exynos850.
- Qualcomm Eliza camera, camera-BIST, GPU, and video clks
- Qualcomm Hawi / Maili camera and GPU controllers
- Qualcomm Kuno global, RPMh
- Qualcomm MSM8952 global, RPM
- Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
- Qualcomm IPQ5210 / IPQ9650 network clocks
- i.MX93 350 MHz fractional-N GP-PLL for display
- i.MX pll14xx spread-spectrum clock generation
- Amlogic A9 SCMI clock controller
- Allwinner single-divider "update bit" support
- EN7523 Serdes port selection"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
clk: imx: pll14xx: support spread spectrum clock generation
clk: cdce925: Size the PLL child name buffer for any int
clk: stm32: fix clock array size for STM32MP21
dt-bindings: clock: Convert HiSilicon clocks to DT schema
clk: lmk04832: Handle reset GPIO lookup errors
dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
clk: tegra: bpmp: remove kcalloc
clk: mmp2-audio: add missing PM_CLK dependency
clk: zte: Introduce a driver for zx297520v3 LSP clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap-based clocks
clk: zte: Add Clock registration infrastructure
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
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'clk-tenstorrent' and 'clk-pile' into clk-next
* clk-renesas: (25 commits)
clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS
clk: renesas: rzg2l: Fix internal clock names
clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets
clk: renesas: Add support for RZ/G2M v3.0
clk: renesas: r9a08g046: Add CANFD clocks and resets
clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks
dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
clk: renesas: r8a779g0: Add ZG clocks
clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()
clk: renesas: r9a09g077: Register SYSC regmap
clk: renesas: rcar-gen3: Use FIELD_GET()
clk: renesas: rzv2h: Convert to clk_hw based provider API
clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register()
clk: renesas: r9a08g046: Add PCIe clocks and reset
clk: renesas: Make sure clk_init_data is fully initialized
clk: renesas: r9a08g046: Add clock and reset entries for LVDS
clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
clk: renesas: r9a08g046: Sort macro definitions alphabetically
clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle
...
* clk-samsung:
clk: samsung: acpm: add Exynos850 support
clk: samsung: acpm: introduce driver data for SoC-specific clocks
clk: samsung: Introduce Exynos5515 clock driver
clk: samsung: clk-pll: Add support for pll_309
dt-bindings: clock: Add Exynos5515 SoC
* clk-starfive:
dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator
* clk-tenstorrent:
MAINTAINERS: Update RISC-V Tenstorrent SoC entry
clk: tenstorrent: use regmap_assign_bits() for conditional set/clear
clk: tenstorrent: Fix refcount leak on shared gate clk enable failure
clk: tenstorrent: Assign .num before accessing .hws
* clk-pile: (126 commits)
clk: imx: pll14xx: support spread spectrum clock generation
clk: cdce925: Size the PLL child name buffer for any int
clk: stm32: fix clock array size for STM32MP21
dt-bindings: clock: Convert HiSilicon clocks to DT schema
clk: lmk04832: Handle reset GPIO lookup errors
dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
clk: tegra: bpmp: remove kcalloc
clk: mmp2-audio: add missing PM_CLK dependency
clk: zte: Introduce a driver for zx297520v3 LSP clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap-based clocks
clk: zte: Add Clock registration infrastructure
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
...
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Convert the HiSilicon Hi6220/Hi3660/Hi3670 clock bindings to DT schema
format. Rearrange the binding documents splitting out the stub clock
binding from everything else.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Link: https://patch.msgid.link/20261001212051.2227941-1-robh@kernel.org
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The main oscillator is the only required input clock for the CRU, while
the external CAN and WDT clocks are optional board-level inputs. The
binding currently requires all three clocks, forcing device trees for
boards without these external inputs to add stub fixed-clock nodes for
which no meaningful clock-frequency can be specified.
Allow the clocks and clock-names properties to contain just "osc",
optionally followed by either or both of "can_ext" and "wdt_ext".
Fixes: 155d900e4c7d ("dt-bindings: clock: add Anlogic DR1V90 CRU")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The clock controller of the zx297520v3 Low Speed Peripherals is
relatively clean. One register per device with gates, muxes and resets
and for some devices a divider. There are even bits in the matrix
controller to control propagation of clock lines down to LSP.
The clocks are sorted by register address and I am convinced that the
device list is complete. There are, however, a few more registers that
are likely extra dividers for TDM and I2S devices.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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This controller contains clocks and resets for high speed devices on the
zx297520v3 board and hardware spinlocks that I expect will be necessary
to communicate correctly with the LTE DSP firmware blob.
I don't know much about the hwlocks yet other than that they exist, so
there is no header yet adding meaning to their indices. Presumably that
meaning doesn't exist in hardware and is de facto defined by ZTE's
firmware blobs running on the rprocs.
The zte-zx297520v3-crm driver will instantiate separate MFD children for
clocks and resets, which are handled by separate clock and reset
drivers.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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These SoCs have 3 clock and reset controllers: Top, Matrix and LSP.
Clocks go from oscillator -> top -> matrix -> LSP, with a register in
top controlling most clocks that get passed to matrix and a register in
matrix controlling all the clocks that get passed to LSP.
Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.
The top clock controller is fed by a 26 MHz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.
Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.
The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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The MA35D1 clock controller takes two crystal oscillator inputs from
the board:
- HXT, a high-speed 24 MHz crystal for most of the system
- LXT, a low-speed 32.768 kHz crytal for the RTC and low power modes
So far the binding was expecting a single crystal. The example named it
HXT, but no real definition for it was given. LXT was not even
described. In order to remain backward compatible, we will continue to
allow either one (HXT) or two (HXT then LXT) input clocks. I propose to
give those phandles a name to clarify what these entries expect, but I'm
not listing the clock-names property in the required block, for backward
compatibility. The rates are fixed by the TRM, so even if the second
oscillator is not described, the OS can make an educated guess.
Fixes: 2f8b5eb589cb ("dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller")
Cc: stable@vger.kernel.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-2-48937ee6c9bb@bootlin.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- A bunch of improvements in dt-check-style. Fix various bindings based
on these additional checks.
- Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade,
hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs,
mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and
ti,omap-ocp2scp to DT schema format
- Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO
PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus,
HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC
- Various binding updates to fix schema warnings in .dts files
- Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and
regulator, and mailbox.txt
- Remove the unused of_overlay_remove_all() function
- Fixes for of_check_msi_parent()
- Add "i2c-parent" tracking to fw_devlink
* tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits)
dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller
dt-bindings: iommu: Describe MT8195 infra IRQs
dt-bindings: clock: mediatek: Add MT8516 fallbacks
dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema
dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema
dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema
dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY
of: overlay: remove unused of_overlay_remove_all()
dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema
dt-bindings: bus: Add HiSilicon local bus
dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu
dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC
dt-bindings: vendor-prefixes: add Ambarella
dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings
dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints
dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema
dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema
of/irq: Stop the MSI walk at the first msi-parent
of/irq: Fix device node refcount leak in of_check_msi_parent()
dt-bindings: display: faraday,tve200: Use a level-high interrupt
...
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git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
Pull media updates from Mauro Carvalho Chehab:
- v4l2 core:
- improve subdev and pixformat kAPI;
- fix P010 format info and add Y12 format info;
- add fwnode_graph_for_each_endpoint_scoped();
- New sensor drivers:
- Sony IMX576
- OmniVision OS02G10, OV05C10 and OG0VA1B
- Samsung S5KJN5
- Himax HM1246
- Maxim GMSL2/3: add support for MAX9296A, MAX96717, and MAX96724
- Intel IPU6: add support for IPU7, IPU7.5 and IPU8
- NXP: add support for i.MX95 CSI pixel formatter driver
- ITE: add driver for IT6625/IT6626 HDMI bridge
- Qualcomm: add CSI2 3ph DPHY driver
- Rockchip: add rk3576 MIPI capture vicap driver
- STM32 DCMIPP: Add STM32MP25 subdevices
- Lots of driver fixes and cleanups
* tag 'media/v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (596 commits)
media: i2c: imx576: Fix line length register
media: ov05c10: Remove duplicated writes to analogue gain register
media: ov05c10: Power management fixes
media: ov05c10: Set reset GPIO high when acquiring it
media: ov05c10: Small cleanups
media: maxim-serdes: Disable test pattern generator for now
media: mc: Keep INTERNAL pad flags just for the kernel, for now
media: i2c: imx576: select VIDEO_CCS_PLL to repair build error
media: Documentation: mc: Fix Stream reference
media: i2c: add imx576 image sensor driver
dt-bindings: media: i2c: Add imx576 sensor
media: i2c: maxim-serdes: add MAX9296A driver
media: i2c: remove MAX96714 driver
media: i2c: maxim-serdes: add MAX96724 driver
staging: media: remove MAX96712 driver
arm64: defconfig: disable deprecated MAX96712 driver
media: i2c: maxim-serdes: add MAX96717 driver
media: i2c: remove MAX96717 driver
media: i2c: add Maxim GMSL2/3 deserializer framework
media: i2c: add Maxim GMSL2/3 serializer framework
...
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git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are lots of minor updates for driver subsystems managed through
the soc tree (turris-omnia platform, cache driver, tee drivers,
arm-cci, bus, memory) as well as soc vendor specific drivers
(starfive, xilinx, microchip, nxp, amlogic, imx, renesas, samsung, ti,
nvidia).
The more notable changes are:
- Larger updates for Qualcomm SoCs including support for SM8950
(Maili) SM8975 (Hawi), Glymur, Shikra, and IPQ5424
- Added SoC support for Exynos5515, Tegra264, Tegra410, R8A774A3, and
MT8167 in existing drivers
- Arm SCMI firmware driver support for ACPI PCC transport and module
autoloading of protocol specific drivers
- Apple crash log support for CrgA embedded controller"
* tag 'soc-drivers-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (176 commits)
platform: cznic: turris-omnia-mcu: stop button emulation producers
cache: Make cpu_cache_invalidate_memregion() error out if there are no handlers
soc: mpfs: use kref cleanup on probe failure
arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms
bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port()
bus: arm-cci: Drop CPU node reference in cci_ace_init_ports()
soc: fsl: dpio: Free the IRQ before releasing the I/O object
soc: fsl: dpio: Fix cleanup on IRQ registration failure
bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr
bus: fsl-mc: drop the fwnode links of the dpmacs nodes
soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms()
soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get()
firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7
dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller
dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC
soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove
ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra
firmware: qcom: tzmem: disable SHM bridge for SM7125 platform
soc: qcom: ubwc: Add Kalambo UBWC config
firmware: qcom: scm: Allow QSEECOM on Kalambo CRD
...
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MT8516 topckgen and apmixedsys nodes use the common syscon fallback
form. Add the MT8516 compatibles to the branches that allow the
syscon fallback.
Fixes: cd9fdd06b0e8 ("dt-bindings: arm: mediatek: topckgen: Convert to DT schema")
Fixes: 16a146735df3 ("dt-bindings: arm: mediatek: apmixedsys: Convert to DT schema")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260921232807.3137010-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
More Qualcomm Arm64 DeviceTree updates for v7.4
Introduce the Hawi SoC and MTP, describing its Oryon CPUs, clocks, power
and interconnect topology, storage, PCIe, USB, thermal management and
remote processors. Add the associated CPU, clock and USB bindings.
Add the Valve Steam Frame (Deckard) headset, Lenovo ThinkPad T14s Gen 7,
Advantech SOM-DB5830, Glymur QCB, and IMDT QCS8550 SoM and SBC. Add the
AYN Thor, Odin 2 Mini and Odin 2 Portal, Ayaneo Pocket DS, Retroid Pocket
6 and Pocket Nova gaming devices.
Add Xiaomi Redmi 9T and 11 Lite 5G NE, LeEco Le2, and Motorola One phone
device trees. Add initial support for the MSM8952 binding and General
Mobile vendor prefix, and document the Kalambo SoC and Samsung Galaxy
A52/A72 boards.
Enable Adreno GPUs and thermal cooling on Kaanapali and SM8750 boards.
Expand Nord with LLCC, PMU and multimedia clock controllers, and add
Maili camera and graphics clock bindings. Add camera, SD card, USB,
Type-C, audio clock and PMIC thermal support across the Shikra variants.
Add IPQ9650 PCIe and interconnect support, IPQ5424 watchdog boot status,
and IPQ9574 USB PHY clock and SDHC reset wiring. Enable quad SPI-NAND on
IPQ5332, IPQ5424 and IPQ9574 reference boards.
Rework PCIe PHY and GPIO placement across the older and current SoCs,
correct PCIe WAKE# polarity on affected platforms, and fix SerDes PHY
supplies on the automotive boards. Add GCC CX power domains across the
supported SoCs and enable SDHC inline encryption on Kodiak and Monaco.
Reserve the embedded-controller reset GPIO on X1 laptop platforms to
prevent accidental resets. Add the Lenovo Yoga Slim 7x embedded
controller, and fix PWM backlight and touchscreen support on the Dell
Inspiron 14 Plus 7441.
Enable the MSM8939 Venus accelerator, SM6350 camera subsystem, QCM6490
IPA, Milos bandwidth monitoring, and Glymur SD card. Add DisplayPort
audio on Purwa, improve Monaco Arduino board cooling and controls, and
apply assorted board-level thermal, audio, storage and pinctrl fixes.
* tag 'qcom-arm64-for-7.4-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (208 commits)
arm64: dts: qcom: shikra-cqs/cqm: Add PMIC thermal support for Shikra IQ2390S SoM platform
arm64: dts: qcom: shikra-cqs/cqm: Add PMIC thermal support for Shikra CQ2390M SoM platform
arm64: dts: qcom: pm8005: Add temp alarm node
arm64: dts: qcom: pm4125: Add VADC and temp alarm nodes
arm64: dts: qcom: shikra: Remove cdsp compute-cb@9
arm64: dts: qcom: shikra: fix sdhc interrupts property
arm64: dts: qcom: talos: Add GCC CX power domain
arm64: dts: qcom: sm8750: Add GCC CX power domain
arm64: dts: qcom: sm8650: Add GCC CX power domain
arm64: dts: qcom: sm8550: Add GCC CX power domain
arm64: dts: qcom: sm8450: Add GCC CX power domain
arm64: dts: qcom: sm8350: Add GCC CX power domain
arm64: dts: qcom: sm8250: Add GCC CX power domain
arm64: dts: qcom: sm8150: Add GCC CX power domain
arm64: dts: qcom: sm6350: Add GCC CX power domain
arm64: dts: qcom: sm4450: Add GCC CX power domain
arm64: dts: qcom: sdx75: Add GCC CX power domain
arm64: dts: qcom: sdm670: Add GCC CX power domain
arm64: dts: qcom: sar2130p: Add GCC CX power domain
arm64: dts: qcom: monaco: Add GCC CX power domain
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
TI K3 device tree updates for v7.4
Generic Fixes/Cleanups:
* MMC: Configure the MMC clock pads as OUTPUT across AM62x, AM62A and AM62P
based boards (SK, LP-SK, BeaglePlay, PocketBeagle2, phyCORE, TQMa62xx,
Variscite and Verdin), so the clock pin is driven correctly.
* am62a: Fix the MMC0_CLK pin register address.
* am62*: Add the wakeup R5F nodes to the pre-RAM bootphase, and split the R5F
memory region on AM62A and AM62P.
* am62*: Correct the wkup R5F memory region size on the AM62A, AM62D and AM62P
boards and SoMs that reuse the shared IPC firmware layout.
* k3-pinctrl: Add virtual GPIO select mux macros.
* am62a/am62p/j722s: Fix watchdog comments.
* dt-bindings: Update the audio-refclk binding and the J721E system controller
binding.
SoC Specific features and Fixes:
AM62A:
* Assign on-chip SRAM to the VPU (wave5) node.
AM62P/J722S:
* Add the GPU node.
* Assign on-chip SRAM to the VPU node.
J721S2:
* Add an mmio-sram node to main_navss and assign SRAM to the VPU node.
Board Specific:
AM62x:
* SK: Mark the eMMC as non-removable.
* AM62L EVM: Remove unnecessary internal pull-ups on the MMC0 pins.
* Verdin, Ivy and Zinnia: Fix the main_gpio0/main_gpio1 line-names array sizes
and add the missing SODIMM_84 line name.
AM62A:
* SK: Add an ethernet alias.
AM62P:
* Verdin: Build the Zinnia DTBs.
AM654:
* Base board: Add a power-off delay so the MMC supply is properly power-cycled.
AM67 (J722S):
* Add support for the PHYTEC phyCORE-AM67x SoM, including its bindings.
AM69 (J784S4/J742S2):
* Aquila: Add the Toradex DSI-to-LVDS adapter with the 10.1" V2 display and fix
a typo in the AQUILA_B73 GPIO line name.
* EVM: Set the ACSPCIe refclk to MAIN_PLL2_HSDIV4 for PCIe1.
J7200:
* Common proc board: Add an ethernet alias.
J721S2:
* EVM: Add an audio overlay.
* Common proc board: Add an ethernet alias.
J722S:
* EVM: Switch the audio codec clock from audio_refclk1 to an external clock,
and add an ethernet alias
* tag 'ti-k3-dt-for-v7.4' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: (52 commits)
arm64: dts: ti: k3-am62*: Add wkup R5F nodes to pre-ram bootphase
arm64: dts: ti: k3-am62p: Split r5f memory region
arm64: dts: ti: k3-am62a: Split r5f memory region
arm64: dts: ti: var-som-am62p: Fix wkup R5F memory region size
arm64: dts: ti: k3-am62p5-sk: Fix wkup R5F memory region size
arm64: dts: ti: k3-am62p-verdin: Fix wkup R5F memory region size
arm64: dts: ti: k3-am62a7-sk: Fix wkup R5F memory region size
arm64: dts: ti: k3-am62d2-evm: Fix wkup R5F memory region size
arm64: dts: ti: k3-am62a-phycore-som: Fix wkup R5F memory region size
arm64: dts: ti: Add audio overlay for k3-j721s2-evm
dt-bindings: ti: Update audio-refclk binding and j721e system controller
arm64: dts: ti: k3-am62-verdin-zinnia: Fix main_gpio0/main_gpio1 line names size
arm64: dts: ti: k3-am62-verdin-ivy: Fix main_gpio0/main_gpio1 line names size
arm64: dts: ti: k3-pinctrl: Add virtual GPIO select mux macros
arm64: dts: ti: k3-am62p-j722s-common-main: Assign SRAM to VPU node
arm64: dts: ti: k3-am62a-main: Assign SRAM to VPU node
arm64: dts: ti: k3-j721s2-main: Assign SRAM to VPU node
arm64: dts: ti: k3-j721s2-main: Add mmio-sram node to main_navss
arm64: dts: ti: k3-am62-verdin: fix main_gpio0/main_gpio1 line names size
arm64: dts: ti: k3-am69-aquila: fix AQUILA_B73 gpio-line-names typo
...
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
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clk-for-7.4
Merge the Maili camera clock controller binding through a topic branch
to avoid the merge conflicts with the DeviceTree branch that has taken
other changes to this same file.
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Add the compatible string for the IPQ5210 CMN PLL clock controller and
the dt-bindings clock ID header for IPQ5210.
The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network
subsystem), PPE (packet process engine), and PON (passive optical
network) hardware blocks. It also supplies a raw EPHY output clock for
the integrated Ethernet PHY and several gated fixed-rate outputs to
Ethernet PHY and switch devices.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-2-aec5ed642f4f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Document RPMHCC bindings for clock rpmh driver on Qualcomm SM7250 SoC.
Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/linux-arm-msm/20260821154030.2514-1-sreeshankar0910@gmail.com
Link: https://patch.msgid.link/20260816131646.10551-3-sreeshankar0910@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add bindings for the Peripheral-3 clock and reset generator (PER3CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the Peripheral-2 clock and reset generator (PER2CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the Peripheral-1 clock and reset generator (PER1CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the Peripheral-0 clock and reset generator (PER0CRG)
on the JHB100 RISC-V SoC by StarFive Ltd.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the System-2 clocks and reset generator (SYS2CRG) on
JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the System-1 clocks and reset generator (SYS1CRG) on
JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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Add bindings for the System-0 clocks and reset generator (SYS0CRG) on
JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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arm64-for-7.4
Merge the Maili clock controller from a topic branch to avoid merge
conflicts with the clock branch, since previous changes to this file has
been merged to both branches.
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Add the Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC,
which is responsible for clock and reset management.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert the Texas Instruments DM816 FAPLL clock binding from plain text
to YAML DT schema.
The text documented #clock-cells to be set as 0, while the example and
existing dt and driver require it to be 1. The schema now strictly
enforces #clock-cells = <1>.
Properties clock-indices and clock-output-names are documented in the
binding and added as required as driver strictly requires it and existing
dt already use this property.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260717-ti-fapll-clock-v1-1-1b684cb2543b@gmail.com
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert the Texas Instruments DM814x ADPLL clock binding to DT schema
format. Add 'clock-output-names' as required which was missing in
legacy binding, as the driver (clk-adpll.c) mandates it and fails
probing if it is missing.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert the IP driver portion of the DRA7 ATL (Audio Tracking Logic)
binding from the freeform text binding to dt-schema. Together with
ti,dra7-atl-clock.yaml this fully replaces dra7-atl.txt.
ti,hwmods is marked deprecated as modern DTS uses ti,sysc target-module
wrappers and the property is absent from current dra7-l4.dtsi.
bws/aws maximum set to 15 per the 16 mux sources in
dt-bindings/clock/ti-dra7-atl.h.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert the clock output portion of the DRA7 ATL (Audio Tracking Logic)
binding from text to DT schema. property clock-output-names is added
that is used by existing dts/dtsi.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert TI da850-pll binding from legacy text to dt schema.
No functional change is introduced during conversion.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: David Lechner <david@lechnology.com>
Link: https://lore.kernel.org/r/20260717-ti-pll-v1-1-f6f9ba8c9b5e@gmail.com
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Convert the Texas Instruments Palmas 32KHz clock bindings
to DT schema.
During the conversion, the node name in the example was updated
from 'palmas_clk32k@0' to 'clock-controller'. The old example
contained a unit address without a 'reg' property, which causes
dtc compilation warnings.
Signed-off-by: Eduard Bostina <egbostina@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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Add ti,j721s2-audio-refclk as a supported compatible string in the
ti,am62-audio-refclk binding. J721S2 uses the same audio reference
clock IP block first introduced on AM62. Per writing-bindings
guidelines, the J721S2-specific compatible is added as the primary
string with ti,am62-audio-refclk as the fallback.
Also extend the ti,j721e-system-controller clock-controller@ child
pattern to accept audio-refclk schemas alongside ehrpwm-tbclk via a
oneOf constraint, fixing the alphanumerical ordering of $refs.
Signed-off-by: Moteen Shah <m-shah@ti.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260923111604.4040417-2-m-shah@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
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Maili camcc is a derivative of Hawi camcc with minor changes, and
hence reuses the Hawi camcc driver. Maili cambistmclkcc is the same
as Kaanapali cambistmclkcc and falls back to it. Add the compatibles
for the camera clock controllers on the Qualcomm Maili SoC.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260922-maili_camcc-v4-1-87704b664dde@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SDX75 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-13-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the QCS8300 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-12-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SM6350 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-11-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SM4450 GCC are supplied by the RPMh CX
power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh
may undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-10-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SM8750 and Kaanapali GCCs are supplied by the
RPMh CX power domain. Model that parent domain in the GCC binding so the
provider can describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Fixes: 342d2a607450 ("dt-bindings: clock: qcom: Add Kaanapali Global clock controller")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-9-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SM8650 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-8-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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The GDSCs provided by the SM8550 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-7-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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|
The GDSCs provided by the QCS615 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-6-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
The GDSCs provided by the SM8450 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-5-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
The GDSCs provided by the SM8350 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-4-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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|
The GDSCs provided by the SM8250 GCC are supplied by the RPMh CX power
domain. Model that parent domain in the GCC binding so the provider can
describe the dependency in devicetree.
Add a single CX power-domain entry to the binding and make it required.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-3-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Describe the CX power-domain dependency for SM8150 GCC and require it in
the binding.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-2-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Require the CX power-domain dependency for SDM845 and SDM670 GCCs.
Without this dependency, GCC GDSC consumers cannot vote for CX and RPMh may
undervolt it.
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-qcom-tie-cx-to-gcc-v5-1-38732033e5b5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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'20260801-nord_videocc_camcc-v2-1-674d7718e41f@oss.qualcomm.com' into HEAD
Merge the Nord video and camera clock controller bindings from a topic
branch, in order to use these in DeviceTree source.
|
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Merge Hawi camera clock controller from topic branch to gain access to
constants.
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Merge Hawi and Maili GPU clock controller bindings through topic branch
to gain access to DeviceTree constants.
|
