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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-08-11 23:28:44 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2026-08-12 09:32:32 +0530 |
| commit | eaed815ca3483c227e4ec80b86d1b3ce5c2508be (patch) | |
| tree | 6636495fb38478d88c63bd1be68a3f1f213493aa /tools/perf/scripts/python | |
| parent | 9ac3ee6c0f92cd09893bd442964fb6b0d6813b5e (diff) | |
| download | linux-eaed815ca3483c227e4ec80b86d1b3ce5c2508be.tar.gz linux-eaed815ca3483c227e4ec80b86d1b3ce5c2508be.zip | |
drm/i915/lt_phy: program DDI_CLK_VALFREQ with DDI clock frequency
DDI_CLK_VALFREQ is programmed with the port clock, which for DP is the
symbol clock computed assuming 8b/10b encoding (link_rate / 10). For
DP 128b/132b (UHBR) rates and for HDMI FRL the port clock needs to
be modified.
DDI_CLK_VALFREQ does not have any functional impact on H/w, it
only records the frequency S/w intends to set.
Use intel_ddi_link_symbol_clock() to write the correct DDI clock in
kHz
Fixes: 5ec58d714935 ("drm/i915/lt_phy: Add .enable_clock hook on DDI")
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260811175844.2613721-4-suraj.kandpal@intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions
