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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-26 16:40:24 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2026-08-27 13:54:51 +0300 |
| commit | 934b9973f712484af9ae8876533d9992fc59cc93 (patch) | |
| tree | 259a4f8e3e48dab24ecd94deb032655ff68a494d /tools/perf/scripts/python | |
| parent | e68e1b80d1639d017bc99857c0c0194df2461334 (diff) | |
| download | linux-934b9973f712484af9ae8876533d9992fc59cc93.tar.gz linux-934b9973f712484af9ae8876533d9992fc59cc93.zip | |
drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2
SKL_CDCLK_PREPARE_FOR_CHANGE == DISPLAY_TO_PCODE_VOLTAGE(3) so
we are currently forcing the voltage level to 3 all the time on
DG2. Remove SKL_CDCLK_PREPARE_FOR_CHANGE from the mask to avoid
this.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260826134033.13976-6-ville.syrjala@linux.intel.com
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions