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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:40:22 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:46:01 +0100 |
| commit | 7c4bda20eb0f150315d19f1b51058820e75d3f3d (patch) | |
| tree | 44ce65525f6937c4e45b918561da8da94c2e5321 /tools/perf/scripts/python | |
| parent | a6b59e65cd7593abc01a7acc47bae5ef180c6f64 (diff) | |
| download | linux-7c4bda20eb0f150315d19f1b51058820e75d3f3d.tar.gz linux-7c4bda20eb0f150315d19f1b51058820e75d3f3d.zip | |
drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder
Add support for the RZ/G3L LVDS encoder driver. It operates in single-link
mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates
from 25 to 87 MHz. The LVDS module cannot be used at the same time as
MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and
the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and
MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS
module.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Tested-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20261001094041.135697-8-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions