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| author | Nemesa Garg <nemesa.garg@intel.com> | 2026-08-18 15:21:49 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2026-08-19 17:17:49 +0530 |
| commit | 600a7c9d40e5e0c5544f42d1c9592c8d15224dc0 (patch) | |
| tree | 48f12db56f389b1d712504fafed5dbb1d3814452 /tools/perf/scripts/python/stackcollapse.py | |
| parent | 5655c87693f6a6006208197a4e3cb29f1253087f (diff) | |
| download | linux-600a7c9d40e5e0c5544f42d1c9592c8d15224dc0.tar.gz linux-600a7c9d40e5e0c5544f42d1c9592c8d15224dc0.zip | |
drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable
icl_plane_disable_sel_fetch_arm() wrote SEL_FETCH_PLANE_CTL = 0 only when
crtc_state->enable_psr2_sel_fetch was set. If a plane was disabled after
selective fetch had been turned off, the guard fired early and left the
register's enable bit set in hardware.
The bit is harmless until selective fetch is re-enabled. When it is, the
hardware resumes fetching for the now-disabled plane and keeps its old DDB
range reserved.
i9xx_cursor_disable_sel_fetch_arm() has the same guard on SEL_FETCH_CUR_CTL
and is fixed the same way.
v2: Add same check for cursor also. [sashiko]
Cc: stable@vger.kernel.org
Fixes: b1f5279b5981 ("drm/i915/psr: Move plane sel fetch configuration into plane source files")
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8739
Assisted-by: GitHub-Copilot:claude-opus-4.6
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://patch.msgid.link/20260818095149.2172935-1-nemesa.garg@intel.com
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions
