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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:40:16 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:46:01 +0100 |
| commit | 47a5825ae7f6ff9aa9c885a263c23743f3f7ad40 (patch) | |
| tree | 32c36c4715120fa0397025915ab79ed578a57b4b /tools/perf/scripts/python/stackcollapse.py | |
| parent | 82e81301ef3b2c7345702c9d5e7374492680df20 (diff) | |
| download | linux-47a5825ae7f6ff9aa9c885a263c23743f3f7ad40.tar.gz linux-47a5825ae7f6ff9aa9c885a263c23743f3f7ad40.zip | |
drm: renesas: rzg2l_mipi_dsi: Add dphyctrl0_init_val to hw_info
Move the DSIDPHYCTRL0 initialization value into the hw_info structure as
dphyctrl0_init_val, allowing SoC-specific D-PHY control register
initialization to be defined per compatible. This prepares the driver for
supporting SoCs that require a different initial DSIDPHYCTRL0 value.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20261001094041.135697-2-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'tools/perf/scripts/python/stackcollapse.py')
0 files changed, 0 insertions, 0 deletions