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| author | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:40:20 +0100 |
|---|---|---|
| committer | Biju Das <biju.das.jz@bp.renesas.com> | 2026-10-01 10:46:01 +0100 |
| commit | abcd3ea0eea0c92756c21ceb660c6ffa0c95d70f (patch) | |
| tree | 46a18cca0c4913461261f5401673a35dcc7459e5 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | b0cd5162dcee45eb0744ee1a59080941fa45fe53 (diff) | |
| download | linux-abcd3ea0eea0c92756c21ceb660c6ffa0c95d70f.tar.gz linux-abcd3ea0eea0c92756c21ceb660c6ffa0c95d70f.zip | |
drm: renesas: rzg2l_mipi_dsi: Add RZ/G3L MIPI DSI support
Add support for the MIPI DSI controller found on the Renesas RZ/G3L
(R9A08G046) SoC. The D-PHY global timing table of RZ/G3L SoC different
compared to the other SoCs. Introduce a dedicated D-PHY global timing
table rzg3l_mipi_dsi_global_timings and wire it up via a new
rzg3l_mipi_dsi_info hw_info variant for RZ/G3L SoC.
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Link: https://patch.msgid.link/20261001094041.135697-6-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions