ACPI: CPPC: Validate and access PCC register layouts

PCC GAS Access Size identifies the subspace while Bit Width identifies
the field size. Support zero-offset byte-multiple fields up to 64 bits
with byte-oriented I/O and explicit little-endian encoding. This accepts
the unaligned 32-bit Delivered Performance Counter in the ACPI
implementation example and read-only widths such as 24 bits. A
per-subspace raw spinlock serializes aliased payload copies made under
the shared side of pcc_lock.

Defer unsupported-field decisions until the package is known. A provided
but inaccessible CPPC Enable or Autonomous Selection Enable control
fails probe. OSPM must set the former and cannot discard the latter
without knowing the hardware autonomous-mode state. An inaccessible
Desired control can be ignored only for immutable autonomous operation.
If both Minimum and Maximum controls are inaccessible, disable the pair
coherently; a one-sided bound fails probe. Other inaccessible optional
controls are marked absent.

Validate PCC ranges after the eight-byte header and reject overlapping
logical ranges when either is writable. Bit-level PCC RMW remains
unsupported.

Probe now rejects or disables unsupported writable PCC widths before
publishing the descriptor. Remove the earlier setter preflights which
repeat that validation.

Fixes: 85b1407bf6d2 ("ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs")
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
Tested-by: Sumit Gupta <sumitg@nvidia.com>
Link: https://patch.msgid.link/20260916162805.1039247-11-christian.loehle@arm.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>

0 files changed, 0 insertions, 0 deletions