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| author | Jesse Zhang <Jesse.Zhang@amd.com> | 2026-10-12 09:28:33 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-10-15 12:46:18 -0400 |
| commit | d65a459dbc9a6c3b051e22c96f73598e34b31bfc (patch) | |
| tree | 42ef68fb6611c7fb4a7f880b7d44b951810b2e3e /scripts/basic/split-include.c | |
| parent | 1b4da805a0ba354a549ce07459c871c17dd94fe0 (diff) | |
| download | linux-d65a459dbc9a6c3b051e22c96f73598e34b31bfc.tar.gz linux-d65a459dbc9a6c3b051e22c96f73598e34b31bfc.zip | |
drm/amdgpu: report the BO alignment in bytes in GEM_LIST_HANDLES
The uapi documents drm_amdgpu_gem_list_handles_entry.alignment as
"physical start_addr alignment in bytes", and GEM_OP
GET_GEM_CREATE_INFO returns the same value in bytes, but
GEM_LIST_HANDLES returns tbo.page_alignment, which is in pages. For a BO
created with a 64 KiB alignment on navi31:
GET_GEM_CREATE_INFO: alignment=65536
GEM_LIST_HANDLES: alignment=16
so a user such as CRIU that recreates BOs from this list uses the wrong
alignment. Convert it to bytes.
Fixes: f9db1fc52ceb ("drm/amdgpu: Add ioctl to get all gem handles for a process")
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit aa4493ae949c13e79aba0731394dd7a7e431342b)
Cc: stable@vger.kernel.org
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions