diff options
| author | Qingwei Hu <qingwei.hu@bytedance.com> | 2026-09-20 03:18:24 -0400 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-10-08 15:24:48 -0600 |
| commit | 7493567982b0786069bf5a0754c96e940ae4978c (patch) | |
| tree | 4dec23e4a79dec2ee2d464067ef12d4e1ea3a68b /scripts/basic/split-include.c | |
| parent | 3776fb1a1b6c22b429bb2683aa2b28cec477cad6 (diff) | |
| download | linux-7493567982b0786069bf5a0754c96e940ae4978c.tar.gz linux-7493567982b0786069bf5a0754c96e940ae4978c.zip | |
riscv: Add Zic64b to cpufeature and hwprobe
Zic64b mandates 64-byte naturally aligned cache blocks and is a
mandatory extension of the RVA22 and RVA23 profiles. Allocate a
RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a
validate callback that requires each cbom/cbop/cboz cache block size to
be 64 bytes when it is present, and export it through hwprobe.
Link: https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059
Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Qingwei Hu <qingwei.hu@bytedance.com>
Co-developed-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Signed-off-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260920-rva23u64-hwprobe-v2-v8-4-5f14bc5c23d3@oss.qualcomm.com
[pjw@kernel.org: updated to apply]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions