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| author | Richard Zhu <hongxing.zhu@nxp.com> | 2026-08-03 11:43:19 +0800 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-09-22 12:14:54 -0500 |
| commit | 5a642c81b31bbd426edceb071ba50839c225220a (patch) | |
| tree | 8707a9a812764048d69df5547338000e8b64c5ac /scripts/basic/split-include.c | |
| parent | 1e184f38851ff6fac0b72bfb7f51db47ed6f257f (diff) | |
| download | linux-5a642c81b31bbd426edceb071ba50839c225220a.tar.gz linux-5a642c81b31bbd426edceb071ba50839c225220a.zip | |
PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
Poor bandwidth margins are observed during i.MX95 Gen3 PCIe tests with the
default MPLLB_BANDWIDTH value (120). The margins worsened across voltage
and temperature (VT) variations and different test matrices, potentially
causing link stability issues.
Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant
improvement in bandwidth margins across all VT conditions and test
scenarios.
Implement PHY register write helper function and configure:
- MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
- MPLLB_BW_OVRD_EN to enable the override
This ensures robust PCIe Gen3 performance across all operating conditions.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: added regmap_read() to flush IMX95_PCIE_PHY_CR_PARA_SEL update]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260803034319.992323-1-hongxing.zhu@oss.nxp.com
Diffstat (limited to 'scripts/basic/split-include.c')
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