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| author | Vincent Jardin <vjardin@free.fr> | 2026-09-28 15:48:09 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-10-14 14:32:57 -0500 |
| commit | 1b09807c4addfd488ae4d0083d3b406ecd2e72f6 (patch) | |
| tree | f609f263bed9133cb81b39c79d396d02ad9ae3b1 /scripts/basic/split-include.c | |
| parent | cee9395acd8043be0644b25c34bfa86623f2b935 (diff) | |
| download | linux-1b09807c4addfd488ae4d0083d3b406ecd2e72f6.tar.gz linux-1b09807c4addfd488ae4d0083d3b406ecd2e72f6.zip | |
PCI: layerscape: Enable async probe by default
dw_pcie_wait_for_link() polls for up to PCIE_LINK_WAIT_MAX_RETRIES *
PCIE_LINK_WAIT_SLEEP_MS (10 * 90 ms) per controller.
The controllers are probed one after the other, so, it leads to slow
boot time.
On an LX2160A board with 4 enabled controllers and no link on any of them,
dw_pcie_host_init() took almost 4s. Probing the 4 controllers in parallel
allows to have it down to 1s.
So enable async probe by default.
Signed-off-by: Vincent Jardin <vjardin@free.fr>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260928-for-upstream-pci-layerscape-async-probe-v1-1-76412d887baa@free.fr
Diffstat (limited to 'scripts/basic/split-include.c')
0 files changed, 0 insertions, 0 deletions