MIPS: OCTEON: cvmx-l2c: use the OCTEON II register model on all CN6XXX

The L2 helpers pick between the OCTEON II and the CN3XXX/CN5XXX
register model with OCTEON_IS_MODEL(OCTEON_CN63XX), which matches the
CN63XX only. Every other OCTEON II part - CN66XX, CN68XX, CN61XX -
takes the CN3XXX/CN5XXX branch and touches registers that do not exist
on it: L2C_DBG, L2C_LCKBASE, L2C_LCKOFF and L2C_SPAR4 instead of the
LCKL2 cache operation, the L2C_WPAR_{PPX,IOBX} way-partitioning
registers and L2C_TADX_TAG.

On a CN6635 board cvmx_l2c_lock_line(), called from prom_init() under
CONFIG_CAVIUM_OCTEON_LOCK_L2 to lock the TLB refill and exception
vectors, therefore went through L2C_DBG/L2C_LCKBASE. Whatever those
writes hit inside the L2 controller left it silently dropping stores to
DRAM above 512 MB: a probe that wrote 0x20400000, 0x40000000,
0x80000000 and 0xe0000000 in prom_init read its values back before the
lock block and the old contents right after it, on CCA 0, 2 and 3
alike, while writes below 256 MB and every u-boot "mw" stuck. Since the
cvmx bootmem free list keeps its nodes inside the free blocks
themselves, the kernel's first split above 0x20000000 was lost, the
walk of the free list stopped there, and the board came up with 248 MB
of its 8 GB.

Match the whole CN6XXX family, which is what these register accesses
are keyed to. The CN63XX keeps exactly the same path.

The geometry helpers in this file need the same treatment but not the
same condition; they are handled in the next patch.

Assisted-by: Claude:claude-opus-5
Signed-off-by: Orgad Shaneh <orgads@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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