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| author | Anirudha Sarangi <anirudha.sarangi@amd.com> | 2026-09-28 15:03:03 +0530 |
|---|---|---|
| committer | Thomas Gleixner <tglx@kernel.org> | 2026-10-15 11:59:22 +0200 |
| commit | 675b45ab71f3b17482dde264d6ee7f98690c487c (patch) | |
| tree | 535427ee2a677a6d277f2573eeaab7e01440526d /scripts/Makefile.thinlto | |
| parent | f556f008f704a8777c73fb3a4177dc57c0dbe769 (diff) | |
| download | linux-675b45ab71f3b17482dde264d6ee7f98690c487c.tar.gz linux-675b45ab71f3b17482dde264d6ee7f98690c487c.zip | |
dt-bindings: interrupt-controller: Add Xilinx Versal NET SMMU CSR
Add a device tree binding schema for the Xilinx Versal NET SMMU CSR
(Control and Status Register) interrupt controller.
The SMMU CSR block acts as a vendor-specific interrupt controller
in front of the ARM SMMUv3, providing registers to enable and clear
standard SMMU interrupts such as EVENTQ, CMDQ_SYNC, GERROR and PRIQ.
Interrupts must be acknowledged in this block before being forwarded
to the parent interrupt controller (e.g. GIC).
Co-developed-by: Tushar Nimkar <tushar.nimkar@amd.com>
Signed-off-by: Anirudha Sarangi <anirudha.sarangi@amd.com>
Signed-off-by: Tushar Nimkar <tushar.nimkar@amd.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260928-smmu-changes-v2-v4-1-3c79a14cd806@amd.com
Diffstat (limited to 'scripts/Makefile.thinlto')
0 files changed, 0 insertions, 0 deletions