Merge tag 'renesas-dts-for-v7.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v7.4 (take two)

  - Add PCIe support for the RZ/G3L SoC,
  - Add ADC DMA support for the RZ/T2H and RZ/N2H SoCs,
  - Add initial support for the RZ/G2M v3.0 SoC and the HopeRun HiHope
    RZ/G2M v3.0 board stack,
  - Add USB support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board,
  - Add SPI (MSIOF) and I2C support for the R-Car X5H SoC,
  - Add support for various SolidRun boards based on RZ/G2L, RZ/G2LC,
    RZ/V2L, and RZ/G2UL,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v7.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits)
  arm64: dts: renesas: Add support for solidrun rzg2ul som on hb-ripple
  arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2lc som
  arm64: dts: renesas: Add support for solidrun hb-ripple with rzv2l som
  arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2l som
  arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: Add dsi panel dt overlay
  arm64: dts: renesas: Add support for solidrun rzg2lc som and hb-iiot evb
  arm64: dts: renesas: Add support for solidrun rzv2l som and hb-iiot evb
  arm64: dts: renesas: Add support for solidrun rzg2l som and hb-iiot evb
  dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards
  arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset
  arm64: dts: renesas: r8a779g0: Add PCIe Application/Local register reset
  arm64: dts: renesas: r8a779f0: Add PCIe Application/Local register reset
  arm64: dts: renesas: r8a78000: Add I2C nodes
  arm64: dts: renesas: r8a78000: Add MSIOF nodes
  dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks
  arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support
  arm64: dts: renesas: r9a09g047: Add USB2.0 support
  arm64: dts: renesas: r9a08g046: Add USB2.0 placeholder nodes
  arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub board support
  arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support
  ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>

4 files changed, 92 insertions, 0 deletions

diff --git a/include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h
new file mode 100644
index 000000000000..09121a30e066
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r8a774a3-cpg-mssr.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a774a3 CPG Core Clocks */
+#define R8A774A3_CLK_Z			0
+#define R8A774A3_CLK_Z2			1
+#define R8A774A3_CLK_ZG			2
+#define R8A774A3_CLK_ZTR		3
+#define R8A774A3_CLK_ZTRD2		4
+#define R8A774A3_CLK_ZT			5
+#define R8A774A3_CLK_ZX			6
+#define R8A774A3_CLK_S0D1		7
+#define R8A774A3_CLK_S0D2		8
+#define R8A774A3_CLK_S0D3		9
+#define R8A774A3_CLK_S0D4		10
+#define R8A774A3_CLK_S0D6		11
+#define R8A774A3_CLK_S0D8		12
+#define R8A774A3_CLK_S0D12		13
+#define R8A774A3_CLK_S1D2		14
+#define R8A774A3_CLK_S1D4		15
+#define R8A774A3_CLK_S2D1		16
+#define R8A774A3_CLK_S2D2		17
+#define R8A774A3_CLK_S2D4		18
+#define R8A774A3_CLK_S3D1		19
+#define R8A774A3_CLK_S3D2		20
+#define R8A774A3_CLK_S3D4		21
+#define R8A774A3_CLK_LB			22
+#define R8A774A3_CLK_CL			23
+#define R8A774A3_CLK_ZB3		24
+#define R8A774A3_CLK_ZB3D2		25
+#define R8A774A3_CLK_ZB3D4		26
+#define R8A774A3_CLK_CR			27
+#define R8A774A3_CLK_CRD2		28
+#define R8A774A3_CLK_SD0H		29
+#define R8A774A3_CLK_SD0		30
+#define R8A774A3_CLK_SD1H		31
+#define R8A774A3_CLK_SD1		32
+#define R8A774A3_CLK_SD2H		33
+#define R8A774A3_CLK_SD2		34
+#define R8A774A3_CLK_SD3H		35
+#define R8A774A3_CLK_SD3		36
+#define R8A774A3_CLK_RPC		37
+#define R8A774A3_CLK_RPCD2		38
+#define R8A774A3_CLK_MSO		39
+#define R8A774A3_CLK_CANFD		40
+#define R8A774A3_CLK_HDMI		41
+#define R8A774A3_CLK_CSI0		42
+#define R8A774A3_CLK_CP			43
+#define R8A774A3_CLK_CPEX		44
+#define R8A774A3_CLK_R			45
+#define R8A774A3_CLK_OSC		46
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A774A3_CPG_MSSR_H__ */
diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 7fd09a3fb353..14b3885f2d99 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -10,5 +10,7 @@
 #define R8A78000_CPG_SGASYNCD4_PERW_BUS		0
 #define R8A78000_CPG_SGASYNCD8_PERW_BUS		1
 #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
+#define R8A78000_CPG_MSO_SCP_MAIN		3
+#define R8A78000_CPG_MSOCK_PERW_BUS		4
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h
index 07bd2a7b0150..92c8408dbc57 100644
--- a/include/dt-bindings/power/qcom,rpmhpd.h
+++ b/include/dt-bindings/power/qcom,rpmhpd.h
@@ -32,6 +32,7 @@
 #define RPMHPD_GBX		22
 #define RPMHPD_NSP3		23
 #define RPMHPD_GFX1		24
+#define RPMHPD_NMXC		25
 
 /* RPMh Power Domain performance levels */
 #define RPMH_REGULATOR_LEVEL_RETENTION		16
diff --git a/include/dt-bindings/power/renesas,r8a774a3-sysc.h b/include/dt-bindings/power/renesas,r8a774a3-sysc.h
new file mode 100644
index 000000000000..ddee6812e9a4
--- /dev/null
+++ b/include/dt-bindings/power/renesas,r8a774a3-sysc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
+#define __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A774A3_PD_CA57_CPU0		 0
+#define R8A774A3_PD_CA57_CPU1		 1
+#define R8A774A3_PD_CA53_CPU0		 5
+#define R8A774A3_PD_CA53_CPU1		 6
+#define R8A774A3_PD_CA53_CPU2		 7
+#define R8A774A3_PD_CA53_CPU3		 8
+#define R8A774A3_PD_CA57_SCU		12
+#define R8A774A3_PD_A3VC		14
+#define R8A774A3_PD_3DG_A		17
+#define R8A774A3_PD_3DG_B		18
+#define R8A774A3_PD_CA53_SCU		21
+#define R8A774A3_PD_A2VC1		26
+
+/* Always-on power area */
+#define R8A774A3_PD_ALWAYS_ON		32
+
+#endif /* __DT_BINDINGS_POWER_RENESAS_R8A774A3_SYSC_H__ */