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authorDave Jiang <dave.jiang@intel.com>2026-10-13 09:01:39 -0700
committerDave Jiang <dave.jiang@intel.com>2026-10-13 09:01:39 -0700
commitd304df5f329302fff4658cd6ed8f93aec4b94d27 (patch)
tree7733586cca27a7347a37e9542eedbed049f6d8c9 /include
parent91320b84095afcaf9e4f676eef5b05346d60eb79 (diff)
parente4478834aa09fd28abaaf774a4bcaa4bbe6804e5 (diff)
downloadlinux-d304df5f329302fff4658cd6ed8f93aec4b94d27.tar.gz
linux-d304df5f329302fff4658cd6ed8f93aec4b94d27.zip
Merge branch 'for-7.4/cxl-dcd' into cxl-for-next
Part 1 of DCD support. Functionality disabled. Documentation/cxl: Document DPA partition layout and ordering rules cxl/core: Enforce partition order/simplify partition calls cxl/mem: Configure dynamic capacity interrupts cxl/pci: Factor out interrupt policy check cxl/events: Split event msgnum configuration from irq setup cxl/cdat: Gather DSMAS data for DCD partitions cxl/mem: Read dynamic capacity configuration from the device cxl/mbox: Flag support for Dynamic Capacity Devices (DCD)
Diffstat (limited to 'include')
-rw-r--r--include/cxl/cxl.h29
1 files changed, 28 insertions, 1 deletions
diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
index 802b143de83d..1c04a7823f64 100644
--- a/include/cxl/cxl.h
+++ b/include/cxl/cxl.h
@@ -130,9 +130,30 @@ struct cxl_dpa_perf {
int qos_class;
};
+/*
+ * Partitions share one flat DPA space in a fixed order:
+ *
+ * DPA 0 end
+ * +---------------+---------------+---------------------------+
+ * | ram | pmem | dynamic_ram_1 |
+ * +---------------+---------------+---------------------------+
+ * part[0] part[1] part[2]
+ *
+ * The static ram and pmem partition order is mandated by CXL r4.0
+ * 8.2.10.9.2.1 "Get Partition Info" (opcode 4100h), Table 8-310: volatile
+ * capacity starts at DPA 0 and persistent capacity starts at the DPA
+ * immediately following it. A dynamic partition has no such
+ * requirement -- 8.2.10.9.9.1 "Get Dynamic Capacity Configuration"
+ * (opcode 4800h), Table 8-347, only requires the DC Region Base to be
+ * 256MB aligned -- but Linux follows that precedent and requires it to
+ * start at the DPA immediately following static capacity: after pmem,
+ * after ram on a device with no pmem, or at DPA 0 on a device with no
+ * static capacity at all. cxl_configure_dcd() enforces it.
+ */
enum cxl_partition_mode {
CXL_PARTMODE_RAM,
CXL_PARTMODE_PMEM,
+ CXL_PARTMODE_DYNAMIC_RAM,
};
/**
@@ -140,14 +161,20 @@ enum cxl_partition_mode {
* @res: shortcut to the partition in the DPA resource tree (cxlds->dpa_res)
* @perf: performance attributes of the partition from CDAT
* @mode: operation mode for the DPA capacity, e.g. ram, pmem, dynamic...
+ * @handle: DSMAS handle that represents this partition
+ * @shareable: Is the partition shareable (from its CDAT DSMAS entry)
+ * @read_only: Is the partition read-only (from its CDAT DSMAS entry)
*/
struct cxl_dpa_partition {
struct resource res;
struct cxl_dpa_perf perf;
enum cxl_partition_mode mode;
+ u8 handle;
+ bool shareable;
+ bool read_only;
};
-#define CXL_NR_PARTITIONS_MAX 2
+#define CXL_NR_PARTITIONS_MAX 3
/**
* struct cxl_dev_state - The driver device state