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| author | Jouni Högander <jouni.hogander@intel.com> | 2026-11-02 12:00:49 +0200 |
|---|---|---|
| committer | Joonas Lahtinen <joonas.lahtinen@linux.intel.com> | 2026-11-11 10:15:01 +0200 |
| commit | 4247f4e2c10eac8c17fc23c2db0e14911b1ba5ff (patch) | |
| tree | 10df0b9fb34a9b9e7d3ff04af525d8726681df75 /drivers/gpu | |
| parent | f1f5942c3fdac3bb553d0019f60d11ca35f9b836 (diff) | |
| download | linux-4247f4e2c10eac8c17fc23c2db0e14911b1ba5ff.tar.gz linux-4247f4e2c10eac8c17fc23c2db0e14911b1ba5ff.zip | |
drm/i915/psr: Re-arm PSR after flush
An ORIGIN_FLIP flush can clear the last busy frontbuffer bits without
queuing the work that re-arms PSR.
Queue the re-arm work after each flush when PSR is inactive and no
frontbuffers are busy.
Move also pipe_frontbuffer_bits ==0 check to done right after pipe
frontbuffer bits are figured out. Anyways nothing is currently done after
in intel_psr_flush if the bits are 0.
v2: Do not re-activate PSR on other pipe frontbuffer bits.
Fixes: ef39826c12b4 ("drm/i915/display: Fix glitches when moving cursor with PSR2 selective fetch enabled")
Cc: <stable@vger.kernel.org> # v5.16+
Tested-by: Ambica Pramod <ambica.pramod@intel.com>
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patch.msgid.link/20261102100051.272137-3-jouni.hogander@intel.com
(cherry picked from commit 731ed8af13bdead02924b39a8c01d5f60d6a2e68)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_psr.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ad57a1209825..5bb9432e8deb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3669,9 +3669,6 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) */ intel_psr_force_update(intel_dp); } - - if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) - queue_work(display->wq.unordered, &intel_dp->psr.work); } /** @@ -3704,6 +3701,10 @@ void intel_psr_flush(struct intel_display *display, pipe_frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); + + if (pipe_frontbuffer_bits == 0) + goto unlock; + intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; /* @@ -3718,13 +3719,14 @@ void intel_psr_flush(struct intel_display *display, psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits); if (origin == ORIGIN_FLIP) - goto unlock; - - if (pipe_frontbuffer_bits == 0) - goto unlock; + goto rearm; /* By definition flush = invalidate + flush */ _psr_flush_handle(intel_dp); + +rearm: + if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) + queue_work(display->wq.unordered, &intel_dp->psr.work); unlock: mutex_unlock(&intel_dp->psr.lock); } |