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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x03c
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x040
#define QSERDES_V10_TX_LANE_MODE_1 0x084
#define QSERDES_V10_TX_LANE_MODE_3 0x08c
#define QSERDES_V10_TX_LANE_MODE_4 0x090
#define QSERDES_V10_TX_LANE_MODE_5 0x094
#define QSERDES_V10_TX_PI_QEC_CTRL 0x0e4
#define QSERDES_V10_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V10_RX_UCDR_SO_GAIN 0x014
#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x04c
#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x050
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0x0c4
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0x0c8
#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0x0cc
#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0x0d8
#define QSERDES_V10_RX_GM_CAL 0x0dc
#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0x0f8
#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
#endif
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