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/* SPDX-License-Identifier: MIT */
/*
* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __LOG_RING_H__
#define __LOG_RING_H__
#include "aca.h"
#include "ras_cper.h"
#define MAX_RECORD_PER_BATCH 32
#define RAS_LOG_SEQNO_TO_BATCH_IDX(seqno) ((seqno) >> 8)
enum ras_log_event {
RAS_LOG_EVENT_NONE,
RAS_LOG_EVENT_UE,
RAS_LOG_EVENT_DE,
RAS_LOG_EVENT_CE,
RAS_LOG_EVENT_POISON_CREATION,
RAS_LOG_EVENT_POISON_CONSUMPTION,
RAS_LOG_EVENT_RMA,
RAS_LOG_EVENT_MCE,
RAS_LOG_EVENT_BOOT,
RAS_LOG_EVENT_CPU_RAS,
RAS_LOG_EVENT_COUNT_MAX,
};
struct ras_aca_reg {
uint64_t regs[ACA_REG_MAX_COUNT];
};
struct ras_cpu_mce {
u64 regs[ACA_REG_MAX_COUNT - 1];
u32 apic_id;
u16 bank;
u16 reserved;
};
#define RAS_CPER_BOOT_RAW_DATA_SIZE 80
#define RAS_BOOT_CTX_VALID_APIC_ID BIT(0)
struct ras_boot_err_ctx {
u8 section_type[16];
u32 error_severity;
u16 reg_ctx_type;
u16 reg_arr_size;
u32 msr_addr;
u16 raw_data_size;
u16 flags;
u64 apic_id;
u64 mm_reg_addr;
union {
u64 regs[CPER_OAM_MAX_COUNT];
u8 raw_data[RAS_CPER_BOOT_RAW_DATA_SIZE];
};
};
union ras_log_body {
struct ras_aca_reg aca_reg;
struct ras_cpu_mce cpu_mce;
struct ras_boot_err_ctx boot_err_ctx;
};
struct ras_log_info {
uint64_t seqno;
uint64_t timestamp;
enum ras_log_event event;
uint32_t size;
union ras_log_body body;
};
struct ras_log_batch_tag {
uint64_t batch_id;
uint64_t timestamp;
uint32_t sub_seqno;
};
struct ras_log_ring {
void *ras_log_mempool;
struct radix_tree_root ras_log_root;
spinlock_t spin_lock;
uint64_t mono_upward_batch_id;
uint64_t last_del_batch_id;
int logged_ecc_count;
};
struct ras_log_batch_overview {
uint64_t first_batch_id;
uint64_t last_batch_id;
uint32_t logged_batch_count;
};
struct ras_core_context;
int ras_log_ring_sw_init(struct ras_core_context *ras_core);
int ras_log_ring_sw_fini(struct ras_core_context *ras_core);
struct ras_log_batch_tag *ras_log_ring_create_batch_tag(struct ras_core_context *ras_core);
void ras_log_ring_destroy_batch_tag(struct ras_core_context *ras_core,
struct ras_log_batch_tag *tag);
int ras_log_ring_add_log_event(struct ras_core_context *ras_core,
enum ras_log_event event,
void *data, uint32_t size, struct ras_log_batch_tag *batch_tag);
int ras_log_ring_get_batch_records(struct ras_core_context *ras_core, uint64_t batch_idx,
struct ras_log_info *log_arr, uint32_t arr_num);
int ras_log_ring_get_batch_overview(struct ras_core_context *ras_core,
struct ras_log_batch_overview *overview);
#endif
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