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https://gitlab.freedesktop.org/drm/rust/kernel into drm-next
DRM Rust changes for v7.4-rc1
- Cross-subsystem:
- I/O (shared from driver-core tree via signed tag rust-io-7.4-rc1):
- Reimplement register!() as a procedural macro, require matching
base types for register access, and replace relative registers
with typed I/O projections. Convert Nova, Tyr and the PCI sample
- Add AsRepr/AsReprMut conversions for I/O on compatible wrapper
types and transmute helpers with deferred size checks
- DMA (shared from driver-core tree via signed tag rust-dma-7.4-rc1):
- Tie Coherent, CoherentBox and CoherentHandle to the device's bound
lifetime, and allow scoped debugfs files backed by non-'static
data
- Allow auxiliary registration-data closures to return covariant
sub-fields and add UserSliceWriter::write_truncated()
- Implement Send and Sync for MapleTree
- Add PCI resource_flags() and IORESOURCE_MEM_64, and convert PCI IRQ
flags to impl_flags!()
- Add I/O view cast() with compile-time size and alignment checks
- DRM:
- Add Rust dma_fence abstractions with separate producer (DriverFence)
and consumer (Fence) types, per-context sequencing, signal callbacks
and preallocation. Additional backend operations remain follow-up
work.
- Initialize DRM registrations and their data in place, removing a
separate allocation
- Drop the unused flags argument from drm::Registration::new()
- Nova:
- UAPI and Cross Module API:
- Add NovaCoreApi and a lifetime-bound handle for auxiliary child
drivers, carried in nova-drm registration data
- Expose a render node and extensible INFO ioctl reporting GPU
architecture, opaque chip ID, usable VRAM and VRAM BAR sizes,
full and short GPU names, and GID, with size discovery and
truncation to the userspace buffer size
- Move BAR-size queries into GPU info, removing GETPARAM and
changing the UAPI
- PRAMIN access:
- Add typed CPU access to VRAM through the movable 1 MiB BAR0
PRAMIN window, with per-architecture support from Turing through
Blackwell
- Add GpuMm centralized memory manager, VramAddress type, aperture
documentation and optional probe-time self-tests under
CONFIG_NOVA_CORE_SELFTESTS
- GPU virtual memory and BAR1:
- Add VRAM buddy allocation, TLB flushing, MMU v2/v3 page-table
types with trait-based generics (PteOps, PdeOps, DualPdeOps,
MmuConfig) and a generic walker
- Add maple-tree virtual address tracking and multi-page mapping,
separating allocation from mapping execution
- Add CPU access to mapped VRAM through BAR1 and memory-management
self-tests; handle 64-bit BAR0 when locating BAR1
- GPU interrupts and GSP events:
- Add GIN (GPU Interrupt and Notification) interrupt-tree support
with MSI-X, MSI fallback and per-architecture rearming
- Drain GSP events between commands via a threaded SWGEN0 handler
- Report OS errors, robust-channel notifications and unknown
messages without aborting command waits; hold the queue lock and
use one deadline per wait
- Disable GSP event interrupts on persistent falcon faults or
drain errors
- Add a delivery/rearm self-test, interrupt-tree KUnit coverage
and interrupt-controller documentation
- GSP messaging fixes:
- Queue setup RPCs before GSP-RM boot
- Correct DMA barriers in both queue directions
- Firmware and transport:
- Extract a reusable radix3 buffer mapper; zero-pad page-table
levels to whole pages to prevent booter reads of stale padding
- Correct GSP-FMC naming and boot-flow documentation
- Set MCTP header version 1 for FSP messages and retain the
command queue's BAR0 reference
- Resource handling:
- Replace unnecessary BarUser reference counting with in-place
ownership and borrowed access; consolidate probe initialization
- Declare an unlimited DMA maximum segment size
- Tyr:
- Use bitfield!() for firmware section flags and memory attributes
that do not describe registers
- Zero unsupported and newly added GPU-info fields, and limit the
doorbell array to 17 entries to fit the mapped register region
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: "Danilo Krummrich" <dakr@kernel.org>
Link: https://patch.msgid.link/DM371PN4TBJT.3LY1B0EYWSI4@kernel.org
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The kernel provides impl_flags! for declaring a bitmask type alongside
the enum of its individual flags, generating the bit operators and the
containment queries.
IrqTypes open-coded that pattern with a with() builder, so a caller
naming two interrupt types chained two calls onto IrqTypes::default().
Declare both types through impl_flags!, so the same set reads as
IrqType::Msi | IrqType::MsiX.
Suggested-by: Gary Guo <gary@garyguo.net>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260930034148.590687-2-jhubbard@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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IrqVectorRegistration::index() accepts a usize, but pci_irq_vector()
takes an unsigned int. On 64-bit architectures, casting an index larger
than u32::MAX wraps it before the PCI core can validate it. In
particular, u32::MAX + 1 becomes zero and can resolve to the first
allocated vector.
Use a checked conversion and return EINVAL when the index cannot be
represented by the C API.
Fixes: 2fb7755b0a7e ("rust: pci: resolve IRQ in index() and embed IrqRequest in IrqVector")
Signed-off-by: Sophon Zhang <aiqubits@hotmail.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Link: https://patch.msgid.link/20260901-fix-pci-irq-vector-index-truncation-v4-1-f94aa6932fd9@hotmail.com
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Add irq_type() on IrqVectorRegistration and IrqVector, wrapping the new
pci_irq_type() C function. A driver whose interrupt acknowledgment
depends on the type (MSI-X vs MSI vs INTx) queries it here rather than
assuming which type the PCI core selected.
Tested-by: John Hubbard <jhubbard@nvidia.com>
Suggested-by: John Hubbard <jhubbard@nvidia.com>
Link: https://lore.kernel.org/all/20260808031120.363869-4-jhubbard@nvidia.com/
Reviewed-by: Gary Guo <gary@garyguo.net>
Link: https://patch.msgid.link/20260813165234.620555-6-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Remove the thin wrappers on Device<Bound> that only forwarded to
irq::Registration::new() and irq::ThreadedRegistration::new(). With
IrqVector embedding a resolved IrqRequest, the conversion is infallible
and drivers call irq::Registration::new(vector.into(), ...) directly.
Unlike the platform equivalents, which combine a fallible IRQ lookup
with handler registration, the PCI wrappers add no value beyond
namespacing. They also introduce a redundant device reference.
IrqVector already carries a device borrow through its embedded
IrqRequest, yet the wrappers required a second, potentially unrelated,
&self receiver.
Tested-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Link: https://patch.msgid.link/20260813165234.620555-4-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Move the pci_irq_vector() call from the TryInto<IrqRequest> impl into
IrqVectorRegistration::index(), so the IRQ number is resolved eagerly.
IrqVector now embeds the resolved IrqRequest and a reference to the
IrqVectorRegistration. The conversion to IrqRequest is infallible, which
removes the need for pin_init_scope() in request_irq() /
request_threaded_irq().
Tested-by: John Hubbard <jhubbard@nvidia.com>
Inspired-by: John Hubbard <jhubbard@nvidia.com>
Link: https://lore.kernel.org/all/20260808031120.363869-3-jhubbard@nvidia.com/
Reviewed-by: Gary Guo <gary@garyguo.net>
Link: https://patch.msgid.link/20260813165234.620555-3-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Convert IrqVectorRegistration from a devres-managed internal type to a
lifetime-annotated type that owns the PCI interrupt vector allocation.
Dropping it frees the vectors.
IrqVector gains a reference to the IrqVectorRegistration it was derived
from. Since index() borrows the registration, the compiler prevents the
allocation from being dropped while any IrqVector (and hence any
irq::Registration built from it) is still live.
alloc_irq_vectors() returns IrqVectorRegistration<'_> directly, giving
drivers explicit control over the allocation lifetime, which is needed
by net and block drivers that re-allocate vectors at runtime, e.g.
during queue reconfiguration or device recovery.
Tested-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Link: https://patch.msgid.link/20260813165234.620555-2-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Adapt the IRQ registration to work with the Higher-Ranked Lifetime Types
(HRT) device driver architecture introduced in commit 2c7c65933600
("Merge patch series "rust: device: Higher-Ranked Lifetime Types for
device drivers"").
With HRT, driver structs carry a lifetime parameter tied to the device
binding scope, allowing device resources such as pci::Bar<'bar> to be
held directly rather than through Devres indirection. However, the IRQ
abstraction required Handler: Sync + 'static, preventing handlers from
embedding lifetime-parameterized resources.
Remove the 'static bound from Handler and ThreadedHandler and replace
the Devres<RegistrationInner> indirection with direct request_irq() /
free_irq() calls in the constructor and PinnedDrop. Registration<'a, T>
stores the IrqRequest<'a>, which structurally ties it to the device
binding scope.
Also remove the &Device<Bound> parameter from the handler callbacks,
since handlers that need device access can embed it in their own type.
IRQ handlers can now directly own device resources:
struct IrqHandler<'irq> {
bar: pci::Bar<'irq, BAR_SIZE>,
}
impl irq::Handler for IrqHandler<'_> {
fn handle(&self) -> IrqReturn {
let stat = self.bar.read(regs::STAT);
...
}
}
This eliminates the indirection previously required for IRQ handlers to
access device resources and aligns with the broader goal of expressing
every registration scoped to a driver binding through compile-time
lifetime bounds.
Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Reviewed-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Alice Ryhl <aliceryhl@google.com>
Link: https://patch.msgid.link/20260719153631.559341-1-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Convert all imports in the PCI Rust module to use "kernel vertical"
style.
With this subsequent patches neither introduce unrelated changes nor
leave an inconsistent import pattern.
While at it, drop unnecessary imports covered by prelude::*.
Link: https://docs.kernel.org/rust/coding-guidelines.html#imports
Reviewed-by: Zhi Wang <zhiw@nvidia.com>
Link: https://patch.msgid.link/20251105120352.77603-1-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Currently request_irq() returns
Result<impl PinInit<irq::Registration<T>, Error> + 'a>
which may carry an error in the Result or the initializer; the same is
true for request_threaded_irq().
Use pin_init::pin_init_scope() to get rid of this redundancy.
Reviewed-by: Alice Ryhl <aliceryhl@google.com>
Link: https://patch.msgid.link/20251103203053.2348783-1-dakr@kernel.org
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Consistently use INTx, as in the description of IrqType::Intx, to refer
to the four legacy PCI interrupts, INTA#, INTB#, INTC#, and INTD#.
Link: https://lore.kernel.org/rust-for-linux/20251015230209.GA960343@bhelgaas/
Link: https://github.com/Rust-for-Linux/linux/issues/1196
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Peter Colberg <pcolberg@redhat.com>
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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Move the PCI interrupt infrastructure to a separate sub-module in order
to keep things organized.
Signed-off-by: Danilo Krummrich <dakr@kernel.org>
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