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28 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
28 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git
28 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git # Conflicts: # Documentation/devicetree/bindings/usb/am33xx-usb.txt # Documentation/devicetree/bindings/usb/da8xx-usb.txt
29 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git # Conflicts: # Documentation/devicetree/bindings/phy/qcom,x1e80100-csi2-phy.yaml
29 hoursMerge branch 'char-misc-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git # Conflicts: # drivers/android/binder_alloc.c # drivers/android/binderfs.c # rust/kernel/miscdevice.rs
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git
29 hoursMerge branch 'watchdog-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
29 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
29 hoursMerge branch 'next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git
29 hoursMerge branch 'next' of git://linuxtv.org/media-ci/media-pending.gitMark Brown
30 hoursMerge branch 'clk-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git
30 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
30 hoursMerge branch 'for-next' of ↵Mark Brown
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
42 hoursMerge branch 'soc/dt' into for-nextAlexandre Belloni
2 daysMerge tag 'renesas-dts-for-v7.4-tag2' of ↵Alexandre Belloni
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v7.4 (take two) - Add PCIe support for the RZ/G3L SoC, - Add ADC DMA support for the RZ/T2H and RZ/N2H SoCs, - Add initial support for the RZ/G2M v3.0 SoC and the HopeRun HiHope RZ/G2M v3.0 board stack, - Add USB support for the RZ/G3E SoC and the RZ/G3E SMARC EVK board, - Add SPI (MSIOF) and I2C support for the R-Car X5H SoC, - Add support for various SolidRun boards based on RZ/G2L, RZ/G2LC, RZ/V2L, and RZ/G2UL, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v7.4-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (34 commits) arm64: dts: renesas: Add support for solidrun rzg2ul som on hb-ripple arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2lc som arm64: dts: renesas: Add support for solidrun hb-ripple with rzv2l som arm64: dts: renesas: Add support for solidrun hb-ripple with rzg2l som arm64: dts: renesas: rzg2l(c)/rzv2l hb-iiot: Add dsi panel dt overlay arm64: dts: renesas: Add support for solidrun rzg2lc som and hb-iiot evb arm64: dts: renesas: Add support for solidrun rzv2l som and hb-iiot evb arm64: dts: renesas: Add support for solidrun rzg2l som and hb-iiot evb dt-bindings: soc: renesas: Add various SolidRun RZ/G2 based boards arm64: dts: renesas: r8a779h0: Add PCIe Application/Local register reset arm64: dts: renesas: r8a779g0: Add PCIe Application/Local register reset arm64: dts: renesas: r8a779f0: Add PCIe Application/Local register reset arm64: dts: renesas: r8a78000: Add I2C nodes arm64: dts: renesas: r8a78000: Add MSIOF nodes dt-bindings: clock: renesas,r8a78000-cpg: Add MSIOF clocks arm64: dts: renesas: r9a09g047e57-smarc: Enable USB2.0 support arm64: dts: renesas: r9a09g047: Add USB2.0 support arm64: dts: renesas: r9a08g046: Add USB2.0 placeholder nodes arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC sub board support arm64: dts: renesas: Add HiHope RZ/G2M v3.0 SoC main board support ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
3 daysMerge branch 'clk-qcom' into clk-nextJerome Brunet
4 daysMerge branches 'arm32-for-7.4', 'arm64-defconfig-for-7.4', ↵Bjorn Andersson
'arm64-fixes-for-7.3', 'arm64-for-7.4', 'clk-fixes-for-7.3', 'clk-for-7.4', 'drivers-fixes-for-7.3' and 'drivers-for-7.4' into for-next
4 daysMerge branch 'soc/drivers' into for-nextArnd Bergmann
* soc/drivers: (133 commits) arm64: enable HAVE_SHARED_GPIOS for all ARM64 platforms bus: arm-cci: Drop cci-control-port node reference in __cci_ace_get_port() bus: arm-cci: Drop CPU node reference in cci_ace_init_ports() soc: fsl: dpio: Free the IRQ before releasing the I/O object soc: fsl: dpio: Fix cleanup on IRQ registration failure bus: fsl-mc: Annotate fsl_mc_io.portal_virt_addr with __counted_by_ptr bus: fsl-mc: drop the fwnode links of the dpmacs nodes soc: fsl: cpm1: tsa: Fix clock leak in tsa_of_parse_tdms() soc: qcom: geni-se: Drop unused icc_ddr parameter from geni_icc_get() firmware: qcom: scm: Allow QSEECOM on ThinkPad T14s Gen 7 dt-bindings: mailbox: qcom: Document Maili CPUCP mailbox controller dt-bindings: spmi: glymur-spmi-pmic-arb: Add compatible for Qualcomm Maili SoC soc: qcom: pmic_pdcharger_ulog: prevent work requeue during remove ASoC: dt-bindings: qcom,apr: Add modem_apps GLINK channel for shikra firmware: qcom: tzmem: disable SHM bridge for SM7125 platform soc: qcom: ubwc: Add Kalambo UBWC config firmware: qcom: scm: Allow QSEECOM on Kalambo CRD firmware: qcom: scm: Allow QSEECOM on the Glymur QCB soc: qcom: stats: Add stats compatible and config for Shikra dt-bindings: soc: qcom: stats: Add compatible for Shikra ...
4 daysMerge branch '20260811-ipq9650_icc-v2-1-55b8efbd62c6@oss.qualcomm.com' into ↵Bjorn Andersson
clk-for-7.4 Merge the IPQ9650 interconnect binding extension through a topic branch to enable the constants to be shared with DeviceTree branches as well.
4 daysdt-bindings: clock: qcom: Add CMN PLL support for IPQ5210 SoCLuo Jie
Add the compatible string for the IPQ5210 CMN PLL clock controller and the dt-bindings clock ID header for IPQ5210. The IPQ5210 CMN PLL supplies configurable clocks to the NSS (network subsystem), PPE (packet process engine), and PON (passive optical network) hardware blocks. It also supplies a raw EPHY output clock for the integrated Ethernet PHY and several gated fixed-rate outputs to Ethernet PHY and switch devices. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com> Link: https://patch.msgid.link/20260906-qcom_ipq5210_cmnpll-v4-2-aec5ed642f4f@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
4 daysdt-bindings: clock: qcom: nord-negcc: Add the secondary QUSB2 PHY resetBartosz Golaszewski
The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but right now only the primary is registered. Add the secondary, which is required by the usb_1 eUSB2 PHY. Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and is instead reset as a whole via NE_GCC_USB20_PRIM_BCR. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://patch.msgid.link/20260901035322.654-2-shengchao.guo@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
4 daysdt-bindings: clock: qcom: Add EMAC CNOC APB clocks for NordTaniya Das
Add the EMAC0 and EMAC1 CNOC APB clock IDs to the SE_GCC clock controller bindings for the Qualcomm Nord SoC. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Tested-by: Shawn Guo <shengchao.guo@oss.qualcomm.com> Link: https://patch.msgid.link/20260824-nords_emac_apb_clk-v1-1-290767386bf5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 daysMerge branch 'clk-amlogic' into clk-nextJerome Brunet
* clk-amlogic: clk: meson: t7: don't mark sys_ampipe_nand as critical dt-bindings: clock: Add Amlogic A9 SCMI clock controller clk: meson: t7: keep the memory fabric clocks running
8 daysdt-bindings: arm: Add the actual power domains on U8500Linus Walleij
This file has been left in an unfinished state just defining the root power domain for the U8500 SoC. Fix it up by adding the actual existing power domains in this SoC. The PRCMU code and old regulator driver is mentioning some *_RET domains, this means "retention" and is a state in the domain and not a domain of its own. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
8 daysdt-bindings: arm: ux500: Drop NR_DOMAINSLinus Walleij
Keep the internal Ux500 PM domain count local to the only driver that uses it. Do not expose this implementation detail through the DT binding header. Assisted-by: LLM Suggested-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Ulf Hansson <ulfh@kernel.org>
10 daysdt-bindings: pinctrl: mediatek,mt6779-pinctrl: Add bindings for MT6735 pin ↵Yassine Oudjana
controller Add DT bindings for the MT6735 pin controller. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Linus Walleij <linusw@kernel.org>
10 daysASoC: dt-bindings: cs35l45: Adds LDPM settingsRicardo Rivera-Matos
Introduce devicetree properties for configuring level dependent power management (LDPM) functionality. Signed-off-by: Ricardo Rivera-Matos <rriveram@opensource.cirrus.com> Link: https://patch.msgid.link/20261001-cs35l45-ldpm-v1-1-545787a5afe5@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
12 daysMerge branches 'clk-tenstorrent' and 'clk-samsung' into clk-nextBrian Masney
12 daysdt-bindings: dma: Add Amlogic A9 SoC DMAXianwei Zhao
Add documentation describing the Amlogic A9 SoC DMA. And add the properties specific values defines into a new include file. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20260903-amlogic-dma-v12-1-f769bc344056@amlogic.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
12 daysdt-bindings: phy: Add nvidia,tegra264-mphyKartik Rajput
Add binding for the MIPI M-PHY on NVIDIA Tegra264 SoCs. The M-PHY is a hardware block with two lanes, l0 and l1, used by the Tegra264 UFS host controller. Signed-off-by: Kartik Rajput <kkartik@nvidia.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260909-tegra264-mphy-v1-1-ce61a80dc065@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
12 daysdt-bindings: arm: qcom,ids: Add SoC ID for SM8950Jingyi Wang
Add the ID for the Qualcomm SM8950 SoC which represents the Maili platform. Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260922-maili-socinfo-v1-1-a82bd7d4ca77@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
12 daysdt-bindings: arm: qcom,ids: Add SoC ID for SM8975Mukesh Ojha
Add the ID for the Qualcomm SM8975 SoC which represents the Hawi platform. Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260923-hawi-socinfo-v1-1-f0d1aaee9323@oss.qualcomm.com Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
12 daysdt-bindings: arm: qcom,ids: Add SoC ID for SM7250Sreeshankar K
Add the ID for the Qualcomm SM7250 SoC. Signed-off-by: Sreeshankar K <sreeshankar0910@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260824150156.1310-2-sreeshankar0910@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-10-02Merge branch 'clk-starfive' into clk-nextBrian Masney
2026-10-02dt-bindings: soc: starfive: Add StarFive JHB100 syscon modulesChanghuang Liang
Add documentation to describe StarFive JHB100 SoC System Controller Registers. Add the PLL clocks for the sys0, per0, and per1 domains under syscon, as well as the PCIe RP reset. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generatorChanghuang Liang
Add bindings for the Peripheral-3 clock and reset generator (PER3CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generatorChanghuang Liang
Add bindings for the Peripheral-2 clock and reset generator (PER2CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generatorChanghuang Liang
Add bindings for the Peripheral-1 clock and reset generator (PER1CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generatorChanghuang Liang
Add bindings for the Peripheral-0 clock and reset generator (PER0CRG) on the JHB100 RISC-V SoC by StarFive Ltd. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generatorChanghuang Liang
Add bindings for the System-2 clocks and reset generator (SYS2CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generatorChanghuang Liang
Add bindings for the System-1 clocks and reset generator (SYS1CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generatorChanghuang Liang
Add bindings for the System-0 clocks and reset generator (SYS0CRG) on JHB100 SoC. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2026-10-02Merge branches 'clk-fixes', 'clk-pile' and 'clk-renesas' into clk-nextBrian Masney
2026-10-02dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controllerStefan Dösinger
The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are, however, a few more registers that are likely extra dividers for TDM and I2S devices. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-10-02dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controllerStefan Dösinger
This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. I don't know much about the hwlocks yet other than that they exist, so there is no header yet adding meaning to their indices. Presumably that meaning doesn't exist in hardware and is de facto defined by ZTE's firmware blobs running on the rprocs. The zte-zx297520v3-crm driver will instantiate separate MFD children for clocks and resets, which are handled by separate clock and reset drivers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-10-02dt-bindings: clk: zte: Add zx297520v3 top clock and reset controllerStefan Dösinger
These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. Clocks go from oscillator -> top -> matrix -> LSP, with a register in top controlling most clocks that get passed to matrix and a register in matrix controlling all the clocks that get passed to LSP. Generally every device has two clocks (one work clock, and one that connects it to the bus, I call it PCLK), two reset bits (I don't know what the difference is - sometimes asserting one is enough to reset the device, sometimes both need to be asserted). PCLK and WCLK are controlled by individual gates. Some devices have a mux and/or a divider for their work clock. Some devices, like the GPIO controller, only have reset bits and no clocks. The top clock controller is fed by a 26 MHz external oscillator and has 4 PLLs to generate other clock rates. ZTE's kernel mostly relies on the boot ROM to set up PLLs, but one LTE-related PLL is not configured on some boards. Therefore my driver contains code to program PLLs. It produces identical settings as the boot ROM for the pre-programmed frequencies. Not all clocks will have an explicit user in the end. I am defining a lot of them simply to shut them off. The boot loader sets up a few of the proprietary timers, which will send regular IRQs (although the kernel of course doesn't need to listen to them). I don't plan to add a driver for the proprietary timer as I see no use for them - the ARM arch timer works just fine. I will add a driver for the very similar proprietary watchdog though. The clock list in this patch is pretty complete but not exhaustive. There are other bits that are enabled, but I couldn't deduce what they are controlling by trial and error. Some of them seem to do nothing. Others cause an instant hang of the board when disabled. It is quite likely that a handful more clocks will be added in the future, but not a large number. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-10-02dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocksMiquel Raynal
The WDT and WWDT muxes have PCLK3/4096 and PCLK4/4096 among their possible parents, but these fixed factor clocks are currently not defined, even though they are needed to properly describe the clock tree. Add them to the bindings. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-4-48937ee6c9bb@bootlin.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2026-10-02dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX defineMiquel Raynal
Drop CLK_MAX_IDX define of MA35D1 include. This is not a binding and should not be placed here. Value is defined in the user driver. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-3-48937ee6c9bb@bootlin.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2026-09-29dt-bindings: clock: add Anlogic DR1V90 CRUJunhui Liu
Add the Clock and Reset Unit (CRU) support for the Anlogic DR1V90 SoC, which is responsible for clock and reset management. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Brian Masney <bmasney@redhat.com>
2026-09-28Merge branch '20260811-ipq9650_icc-v2-1-55b8efbd62c6@oss.qualcomm.com' into ↵Bjorn Andersson
arm64-for-7.4 Merge the IPQ9650 interconnect defines in order to be able to use the provided constants in DeviceTree source.