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https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git
# Conflicts:
# Documentation/devicetree/bindings/usb/am33xx-usb.txt
# Documentation/devicetree/bindings/usb/da8xx-usb.txt
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https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
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https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git
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- TBD
* pci/controller/xilinx-cpm:
PCI: xilinx-cpm: Add support for PCIe RP PERST# signal
dt-bindings: PCI: xilinx-versal-cpm: Add PERST# and reset support
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- Use devm for clocks so they're automatically disabled, unprepared, and
released if errors happen during probe (Yuho Choi)
* pci/controller/xgene:
PCI: xgene: Use managed clock for PCIe controller
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- Flush initiator posted writes before calling IRQ handler to work around a
Meteor Lake erratum, where a DMA completion MSI can arrive before the
completion queue in memory has been updated, resulting in an nvme 30
second stall before a QID timeout and possibly other similar problems
(Rickey Bartlett)
* pci/controller/vmd:
PCI: vmd: Flush initiator posted writes before demuxing interrupts on Meteor Lake
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- Fix the Link Capabilities offset so we read the correct register (Bjorn
Helgaas)
* pci/controller/tegra264:
PCI: tegra264: Fix Link Capabilities register offset
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- Disable refclk on probe failure (Lad Prabhakar)
- Propagate platform_get_irq_byname() errors so probe deferral works
correctly (Lad Prabhakar)
- Tear down INTx handlers if subsequent initialization fails (Lad
Prabhakar)
- Add RZ/G3L (R9A08G046) DT and driver support (Biju Das)
* pci/controller/rzg3s-host:
PCI: rzg3s-host: Add support for RZ/G3L SoC
dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3L SoC
PCI: rzg3s: Fix IRQ domain initialization error handling
PCI: rzg3s: Propagate platform_get_irq_byname() errors
PCI: rzg3s: Disable refclk on probe failure
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- Fix a 64-bit type truncation in mtk_pcie_set_trans_table() to avoid
issues with windows above or larger than 4GB (Sreeraj S Kurup)
* pci/controller/mediatek-gen3:
PCI: mediatek-gen3: Fix 64-bit type truncation in mtk_pcie_set_trans_table()
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- Find INTx DT property by 'interrupt-controller' name instead of assuming
it's the first child node (Zhengping Zhang)
* pci/controller/mediatek:
PCI: mediatek: Find INTx controller by property
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- Limit Max_Read_Request_Size to 256 to avoid hardware erratum (Marek
Vasut)
- Add a .post_deinit() callback to handle dw_pcie_ep_init() failures (Marek
Vasut)
- Rework .additional_common_init() into .init() to simplify flow (Marek
Vasut)
- Add .deinit() and .speed_control() callbacks, both to prepare for R-Car
Gen5 SoC support (Marek Vasut)
- Support PERST# via reset subsystem as well as the existing GPIO support
to prepare for R-Car Gen5 SoCs (Marek Vasut)
- Add DT and driver support for the R-Car Gen 5 X5H (R8A78000) PCIe Gen 4
core (Marek Vasut)
- Drop documentation about obtaining R-Car platform firmware, which is
obsolete now that it's available in the linux-firmware.git repository
(Marek Vasut)
- Add Application/Local register reset DT description and driver support
for both host and endpoint mode (Marek Vasut)
* pci/controller/dwc-rcar-gen4:
PCI: rcar-gen4: Add Application/Local register reset control
dt-bindings: PCI: rcar-gen4-pci-ep: Document Application/Local register reset
dt-bindings: PCI: rcar-gen4-pci-host: Document Application/Local register reset
PCI: rcar-gen4: Drop documentation about obtaining platform firmware
PCI: rcar-gen4: Add support for R-Car X5H PCIe4
PCI: rcar-gen4: Handle PERST# via reset subsystem
PCI: rcar-gen4: Add .speed_control() callback
PCI: rcar-gen4: Add .deinit() callback
PCI: rcar-gen4: Rework .additional_common_init() into .init()
dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car X5H PCIe4 compatible
PCI: rcar-gen4: Use .post_deinit() to handle dw_pcie_ep_init() failures
PCI: dwc: Add dw_pcie_ep_ops->post_deinit() callback
PCI: rcar-gen4: Limit Max_Read_Request_Size to 256 Bytes
# Conflicts:
# drivers/pci/controller/dwc/pcie-rcar-gen4.c
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- Only collect reset GPIOs from PCI bridge DT nodes to avoid stealing
resets used by downstream devices like USB controllers (Christopher
Obbard)
- Block accesses to downstream devices on link down to reduce a storm of
Completion Timeout AER interrupts (Qiang Yu)
- Skip system suspend/resume for firmware-managed PCIe, where firmware
manages clocks, regulators, resets, etc (Mrinmay Sarkar)
- Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0()
(Manivannan Sadhasivam)
* pci/controller/dwc-qcom:
PCI: qcom: Honor IOMMU provider's #iommu-cells in qcom_pcie_config_sid_1_9_0()
PCI: qcom: Skip system suspend/resume for firmware-managed PCIe
PCI: qcom: Block accesses to downstream devices on link down
PCI: qcom: Only check bridge nodes for PERST# GPIOs
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- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
* pci/controller/dwc-keystone:
PCI: keystone: Remove device links to PHY
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- Fix pwrctrl device leak when .probe() PM runtime setup fail (Zhijian Han)
- Fix resource leaks in .probe() error paths (Zhijian Han)
- Improve i.MX95 Gen3 link stability by changing MPLLB_BANDWIDTH from
default 120 to 140 (Richard Zhu)
* pci/controller/dwc-imx6:
PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability
PCI: imx6: Fix resource leaks in probe error paths
PCI: imx6: Fix pwrctrl device leak on PM runtime setup failure
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- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
- Fix optional clock leak when .probe() fails by using
devm_clk_get_optional_enabled() (Felix Gu)
* pci/controller/dwc-dra7xx:
PCI: dra7xx: Fix clock enable leak on probe failure
PCI: dra7xx: Remove device links to PHY
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- Align register macros with Synopsys documentation (Hans Zhang)
- Remove unused PCIE_ATU_UNR_* register definitions; the driver now uses
ATU_* macros instead (Hans Zhang)
* pci/controller/dwc:
PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions
PCI: dwc: Align register macros with Synopsys documentation
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- Fix enum type mismatch warning in LTSSM debugfs (Hans Zhang)
- Remove device links to PHY, which are redundant because the PHY core
itself adds them (Vladimir Oltean)
- Return error (not success) from cdns_plat_pcie_probe() if
pm_runtime_get_sync() or cdns_pcie_ep_setup() failed (Vladimir Oltean)
* pci/controller/cadence:
PCI: cadence: Preserve all error codes in cdns_plat_pcie_probe()
PCI: cadence: Remove device links to PHY
PCI: cadence: Fix enum type mismatch warning in LTSSM debugfs
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- Fix clk and PHY leaks in aspeed_pcie_port_init() error paths (Liu
Zhenlong)
* pci/controller/aspeed:
PCI: aspeed: Fix clk and PHY leak in aspeed_pcie_port_init() error paths
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- Disable PHY on probe failures (Myeonghun Pak)
* pci/controller/aardvark:
PCI: aardvark: Disable PHY on probe failures
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- Add missing headers transitively included by <linux/phy/phy.h> so these
can be removed from linux/phy/phy.h itself (Vladimir Oltean)
* pci/controller/misc:
PCI: Add missing headers transitively included by <linux/phy/phy.h>
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The PCI Express Capability begins at 0x48. Link Capabilities is a 32-bit
register at offset 0xc, and Link Status is a 16-bit register at offset
0x12:
Link Capabilities is at 0x48 + 0xc = 0x54
Link Status is at 0x48 + 0x12 = 0x5a
Previously the driver read Link Capabilities with a 16-bit read from
XTL_RC_PCIE_CFG_LINK_CAPS (0x56), which incorrectly read just the upper
half of the register. When a hotplug-capable port has no link during
probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
width from unrelated bits and requests the wrong interconnect bandwidth.
Correct the Link Capabilities usage by adding a XTL_RC_PCIE_CAP definition
for the base of the PCIe Capability, using the existing PCI_EXP_LNKCAP
(0xc) and PCI_EXP_LNKSTA (0x12) offsets so they're easily searchable, and
reading the entire 32 bits of Link Capabilities.
Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
Based-on-patch-by: Linmao Li <lilinmao@kylinos.cn>
Link: https://lore.kernel.org/20260827093919.2825467-1-lilinmao@kylinos.cn
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260923195719.1933175-2-bhelgaas@google.com
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The PCIE_ATU_UNR_* macros are not used anywhere in the kernel. They
were presumably intended for unrolled iATU register access, but the
driver now uses the ATU_* macros and computes unrolled offsets via
ATU_UNROLL_BASE().
Remove these unused definitions. No functional change intended.
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260911162537.469018-3-18255117159@163.com
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The DWC PCIe register and field macros are inconsistently named and
often do not match the Synopsys DesignWare PCIe Controller Reference
Manual. This makes it harder to cross-reference the code with the
documentation when debugging or maintaining the driver.
As suggested during review, do not add an "_OFF" suffix to the Port Link
Control register: the suffix is ambiguous (offset vs. off) and
unnecessary. Use PORT_LINK_CTRL, and include the register name in its
field macros, e.g. PORT_LINK_CTRL_DLE, PORT_LINK_CTRL_FLM, and
PORT_LINK_CTRL_LC_*.
Align other DWC PCIe controller-internal register macros in the same
spirit by dropping the redundant PCIE_ prefix and using the documented
base names, such as PORT_FORCE_LINK, PORT_AFAC, PORT_LANE_SKEW,
TIMER_CTRL_MAX_FUNC_NUM, PORT_LINK_DEBUG0/1, LINK_WIDTH_SPEED_CTRL,
GEN3_CTRL, GEN3_EQ_CTRL, MULTI_LANE_CTRL, MISC_CONTROL_1,
MSIX_DOORBELL, and the ATU_* registers. Field macros are renamed
consistently so their register association is clear.
This improves code maintainability and eases future reference to the
controller manual.
No functional change intended.
Co-developed-by: Feizhou Yu <yufeizhou201@163.com>
Signed-off-by: Feizhou Yu <yufeizhou201@163.com>
Signed-off-by: Hans Zhang <18255117159@163.com>
[mani: fixed checkpatch warnings by moving comments]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260911162537.469018-2-18255117159@163.com
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advk_pcie_setup_phy() initializes and powers on the PHY before the
emulated bridge and IRQ domains are created. If any of those later
initialization steps or pci_host_probe() fails, probe returns without
powering off or exiting the PHY.
Replace the direct returns with staged cleanup labels. Remove IRQ
domains in reverse order, release the emulated bridge allocation only
after successful initialization, and disable the PHY on every failure
after advk_pcie_setup_phy() succeeds. A setup_phy() failure still
returns directly, so its partial internal cleanup is not repeated.
Fixes: 366697018c9a ("PCI: aardvark: Add PHY support")
Co-developed-by: Ijae Kim <ae878000@gmail.com>
Signed-off-by: Ijae Kim <ae878000@gmail.com>
Signed-off-by: Myeonghun Pak <mhun512@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260910221725.91980-1-mhun512@gmail.com
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The R-Car Gen4 PCIe controller does contain core reset, which puts the
controller back into well-defined state, but it does also tear down the
PCIe link. This is called Application/Local register reset in the
documentation.
Deassert the core reset after the core clock has been enabled, and assert
the core reset in case of error or when shutting down the controller.
This also fixes reinitialization failure of the controller, where if the
controller driver is unbound and bound again via sysfs attributes, the
controller driver will fail to probe the second time because it fails to
access the controller DBI, which returns all zeroes unless the core reset
is toggled. The following commands trigger this fault on R-Car V4H:
$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/unbind
$ echo e65d0000.pcie > /sys/bus/platform/drivers/pcie-rcar-gen4/bind
Fixes: faf5a975ee3b ("PCI: rcar-gen4: Add support for R-Car V4H")
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[mani: added fixes tag and cced noautosel]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: <stable+noautosel@kernel.org> # DTS dependency
Link: https://patch.msgid.link/20260903205153.283553-3-marek.vasut+renesas@mailbox.org
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Add support for R8A78000 (R-Car X5H) PCIe4.
This driver previously supported R-Car Gen4 S4/V4H/V4M. PCIe features
of R-Car X5H PCIe4 are almost all the same. The controller initialization
sequence is slightly different and is factored out into controller-specific
callbacks, in a manner similar to previous R-Car Gen4 handling.
The controller does have a PHY attached to it, but the PHY is operated
by a separate PHY driver. The PHY driver instance binding is handled
in rcar_gen4_pcie_get_resources() and controlled in the aforementioned
controller-specific callbacks.
The controller driver is deliberately using "renesas,rcar-gen5-pcie4"
DT compatible string to discern R-Car X5H PCIe4 controller supported
by this driver, from R-Car X5H PCIe6 controller which will most likely
use a separate driver.
The R-Car X5H PCIe4 controller embeds HDMA instead of EDMA embedded
in the R-Car Gen4 PCIe controller, "dw-edma" driver supports both
DMA variants.
Endpoint mode is currently not implemented for R-Car Gen5 PCIe4.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260921202823.72620-7-marek.vasut+renesas@mailbox.org
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Handle PERST# via both GPIO and reset subsystem. On R-Car Gen4, the PERST#
signal is operated as a GPIO, on R-Car Gen5 it might only be accessible via
SCMI reset via reset subsystem. Support both options. This is a
preparatory work for R-Car Gen5 support.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260921202823.72620-6-marek.vasut+renesas@mailbox.org
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Introduce new rcar_gen4_pcie_drvdata->speed_control() callback and
implement it on R-Car Gen4. The callback implements the second half of what
is currently present in rcar_gen4_pcie_start_link(), and
rcar_gen4_pcie_start_link() does call the .speed_control() callback. This
is a preparatory work for R-Car Gen5 support, where the .speed_control()
implementation is different.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260921202823.72620-5-marek.vasut+renesas@mailbox.org
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Add rcar_gen4_pcie_drvdata->deinit() callback in preparation for R-Car Gen5
support. The .deinit() callback will be used to tear down the PHY on R-Car
Gen5. For now, it does what rcar_gen4_pcie_common_deinit() used to do
directly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260921202823.72620-4-marek.vasut+renesas@mailbox.org
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Rework the current complicated initialization callchain that invokes
host_init->common_init->additional_common_init() for host and
ep_init->common_init->additional_common_init() for endpoint into
simpler host_init->init() and ep_init->init() .
The init callback is now always implemented for all R-Car Gen4 SoCs;
therefore there is no need to check whether the callback is not NULL.
For R-Car S4, the .init() callback is rcar_gen4_pcie_common_init(),
for R-Car V4H and V4M, the .init() callback is implemented using a
new function rcar_gen4_v4h_v4m_pcie_init(), which calls the common
rcar_gen4_pcie_common_init() followed by R-Car V4H- and V4M-specific
hardware initialization. The hardware initialization sequence remains
unchanged.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
[bhelgaas: drop 'dwc' tags, commit log typo]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260921202823.72620-3-marek.vasut+renesas@mailbox.org
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Poor bandwidth margins are observed during i.MX95 Gen3 PCIe tests with the
default MPLLB_BANDWIDTH value (120). The margins worsened across voltage
and temperature (VT) variations and different test matrices, potentially
causing link stability issues.
Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant
improvement in bandwidth margins across all VT conditions and test
scenarios.
Implement PHY register write helper function and configure:
- MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin
- MPLLB_BW_OVRD_EN to enable the override
This ensures robust PCIe Gen3 performance across all operating conditions.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: added regmap_read() to flush IMX95_PCIE_PHY_CR_PARA_SEL update]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260803034319.992323-1-hongxing.zhu@oss.nxp.com
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imx_pcie_probe() leaks both pwrctrl devices and power domains on failure:
- imx_pcie_attach_pd() attaches the "pcie" and "pcie_phy" power domains
and adds device links to them, but nothing detaches the domains or
removes the links on probe failure or deferral, so they leak.
- A failure of devm_pm_runtime_set_active_enabled() returns directly
without destroying the pwrctrl devices.
- A partial failure inside imx_pcie_attach_pd() leaks the power domains
that were already attached.
Add imx_pcie_detach_pd_action() to remove the device links and detach the
power domains in reverse order of acquisition and register it with
devm_add_action_or_reset() so they are released automatically on probe
failure.
Fixes: 2c5768344f88 ("PCI: imx6: Move pci_pwrctrl_create_devices() to imx_pcie_probe()")
Reported-by: sashiko-bot@kernel.org
Link: https://lore.kernel.org/all/20260822013640.182C01F000E9@smtp.kernel.org/
Signed-off-by: Zhijian Han <hanzhijian1991@gmail.com>
[mani: removed the imx_pcie_detach_pd() helper]
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
[bhelgaas: update commit log to match inlining of imx_pcie_detach_pd() into
imx_pcie_detach_pd_action()]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260904012307.3434449-1-hanzhijian1991@gmail.com
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A guest can wait indefinitely in wait_for_response() for the host to
send either a rescind message or a packet completion. If the
host does not send either, the guest can remain blocked with no
diagnostic indicating a reason.
This was observed during a guest kernel upgrade in which the
host-side application handling the PCI channel faulted, causing the
guest to never receive the completion request.
Add a warning in wait_for_response() when the wait exceeds
a timeout so that such a hang is visible in the guest's kernel log
and can be correlated with host-side state.
Suggested-by: Michael Kelley <mhklinux@outlook.com>
Reviewed-by: Naman Jain <namjain@linux.microsoft.com>
Signed-off-by: Sahil Chandna <sahilchandna@linux.microsoft.com>
Signed-off-by: Wei Liu <wei.liu@kernel.org>
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On Hyper-V guests each virtual PCI bus is enumerated by its own
hv_pci_probe() call. The probe performs several synchronous host
request/response exchanges while negotiating the protocol, querying bus
relations, entering D0, and reporting allocated resources. These waits
are latency-bound rather than CPU-bound.
hv_pci registers as an ordinary VMBus driver, so driver_register() walks
matching vPCI buses and probes them sequentially while the driver's
initcall runs. On guests that expose several devices, each through its
own vPCI bus, this serialization adds the host round-trip latencies to
device initialization.
Each bus is described by its own struct hv_pcibus_device, so
independent buses can be probed concurrently. Request asynchronous
probing via PROBE_PREFER_ASYNCHRONOUS, causing the driver core to
schedule matching buses for asynchronous probe work.
On an Azure Standard_L32s_v3 guest with five vPCI targets (four NVMe
controllers and one Mellanox VF), Linux 7.2.3 was tested with one warm-up
and three measured boots per variant. The median interval from the first
hv_pci_probe() entry to the last return decreased from 2847.968 ms to
2786.709 ms, a 61.259 ms (2.15%) improvement.
Co-developed-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Dexuan Cui <decui@microsoft.com>
Signed-off-by: Naman Jain <namjain@linux.microsoft.com>
Reviewed-by: Sahil Chandna <sahilchandna@linux.microsoft.com>
Signed-off-by: Wei Liu <wei.liu@kernel.org>
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The tegra as well as a few dwc PCI controller drivers uses PM runtime
operations without including the required <linux/pm_runtime.h> header.
Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
controllers use the regulator consumer API without including
<linux/regulator/consumer.h>.
pcie-spacemit-k1.c uses of_get_next_available_child() and of_node_put()
without including <linux/of.h>.
It seems these function prototypes were indirectly provided by
<linux/phy/phy.h>, mostly by mistake (none of the functions it exports
need it).
Before the PHY header can drop the unnecessary includes, make sure the
PCI controller drivers include what they use.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260810124315.433448-3-vladimir.oltean@nxp.com
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The blamed commit functionally changed the error path of
cdns_pcie_host_probe(), now cdns_plat_pcie_probe().
When the old code path executed "goto err_get_sync", the PCIe controller
probe function propagated the pm_runtime_get_sync() error code. The new
code doesn't, and returns 0.
Similarly for the "goto err_init" previously triggered by
cdns_pcie_host_init() errors, and now triggered by
cdns_pcie_host_setup() and cdns_pcie_ep_setup() errors. These are not
propagated and will result in probing success, which is incorrect.
Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260810124315.433448-2-vladimir.oltean@nxp.com
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dra7xx_pcie_probe() enables the optional clock but never disables it
when probing fails afterwards.
Switch to devm_clk_get_optional_enabled(), which disables the clock
automatically on failure.
Fixes: 5af9405397bf ("PCI: dra7xx: Get an optional clock")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://patch.msgid.link/20260822-dra7xx-v1-1-23e204d5548b@gmail.com
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This is a full revert of commit 7a4db656a635 ("PCI: dra7xx: Create
functional dependency between PCIe and PHY").
The trouble with this is that a PHY consumer driver dereferences fields
from struct phy, which will become no longer possible.
Since commit 987351e1ea77 ("phy: core: Add consumer device link support")
from 2019, the PHY core also adds a device link to order PHY provider and
consumer suspend/resume operations. The reverted functionality is from 2017
and is redundant with the PHY core now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Aksh Garg <a-garg7@ti.com>
Link: https://patch.msgid.link/20260912161440.1032188-3-vladimir.oltean@nxp.com
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This is a partial revert of the device link pieces from commit
dfb80534692d ("PCI: cadence: Add generic PHY support to host and EP
drivers").
The trouble with this is that a PHY consumer driver dereferences fields
from struct phy, which will become no longer possible.
Since commit 987351e1ea77 ("phy: core: Add consumer device link support")
from 2019, the PHY core also adds a device link to order PHY provider and
consumer suspend/resume operations. The reverted functionality is from
2018 and is redundant with the PHY core now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Aksh Garg <a-garg7@ti.com>
Link: https://patch.msgid.link/20260912161440.1032188-2-vladimir.oltean@nxp.com
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This is a partial revert of the device link pieces from commit
49229238ab47 ("PCI: keystone: Cleanup PHY handling").
The trouble with this is that a PHY consumer driver dereferences fields
from struct phy, which will become no longer possible.
Since commit 987351e1ea77 ("phy: core: Add consumer device link support")
from 2019, the PHY core also adds a device link to order PHY provider and
consumer suspend/resume operations. The reverted functionality is from
2018 and is redundant with the PHY core now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Aksh Garg <a-garg7@ti.com>
Link: https://patch.msgid.link/20260912161440.1032188-4-vladimir.oltean@nxp.com
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Commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators")
inadvertently moved clock enablement before core reset assertion, breaking
PCI device initialization on i.MX6Q Apalis platforms with
ASM1061/ASM1062 SATA controllers connected:
imx6q-pcie 1ffc000.pcie: host bridge /soc/pcie@1ffc000 ranges:
imx6q-pcie 1ffc000.pcie: IO 0x0001f80000..0x0001f8ffff -> 0x0000000000
imx6q-pcie 1ffc000.pcie: MEM 0x0001000000..0x0001efffff -> 0x0001000000
imx6q-pcie 1ffc000.pcie: config reg[1] 0x01f00000 == cpu 0x01f00000
imx6q-pcie 1ffc000.pcie: iATU: unroll F, 4 ob, 4 ib, align 64K, limit 4G
imx6q-pcie 1ffc000.pcie: Link: Only Gen1 is enabled
imx6q-pcie 1ffc000.pcie: Link failed to come up. LTSSM: POLL_CONFIG
imx6q-pcie 1ffc000.pcie: probe with driver imx6q-pcie failed with error -110
NOTE: It is not 100% clear if the issue is specific to the ASM1061/ASM1062
device or on the specific power-up sequence (reset vs cold-power-on).
To fix this regression, restore the original sequence where clocks are
enabled after asserting core reset and configuring the controller type.
Fixes: 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators")
Reported-by: Leonardo Costa <leoreis.costa@gmail.com>
Closes: https://lore.kernel.org/all/bl7i3obu2clzsgeoct2a4mtfhv6typcjdqmgneropf3hpgwve6@n2m5uhlduw57/T/#u
Reported-by: Franz Schnyder <fra.schnyder@gmail.com>
Closes: https://lore.kernel.org/all/t65y5d54axtksbfs7r4olcefqhwm6m4dz3njgnrnf7fcotj74i@o7avoznlafbj/
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
[bhelgaas: move to pci/for-linus for v7.3]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # 7.2+
Link: https://patch.msgid.link/20260813095003.356062-1-hongxing.zhu@oss.nxp.com
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qcom_pcie_config_sid_1_9_0() reads the "iommu-map" property as an array
of fixed four-word {rid-base, phandle, sid, rid-len} entries to program
the BDF to SID translation table. But that layout only holds for an
IOMMU with '#iommu-cells = <1>'. The PCIe SMMUs on these SoCs use
'#iommu-cells = <2>' (SID and mask), so per the pci-iommu binding each
entry is really five cells long.
This used to work only because the DTs were themselves broken. They
described iommu-map with four-cell entries that omitted the SID mask,
which of_map_id() tolerated via its of_check_bad_map() fallback, and the
four-word parsing coincidentally matched that malformed shape.
Since commit ccb2fd725d41 ("of: Respect #{iommu,msi}-cells in maps") the
OF core parses such maps correctly, so the device trees were converted
to proper five-cell entries, e.g. commit c41749e9554d ("arm64: dts:
qcom: sm8250: Fix the PCIe iommu-map entries"). With five-cell entries
the fixed four-word stride slips by one cell for each entry after the
first, so qcom_pcie_config_sid_1_9_0() reads the endpoint mapping's RID
from the preceding entry's length cell and its SID from the phandle cell.
As the RID is the hash key, the endpoint's real RID is never programmed
into the BDF to SID table. Its DMA then hashes to an unprogrammed slot,
gets tagged with SID 0 and the SMMU faults like below on QCS8300:
arm-smmu 15200000.iommu: Unhandled context fault: fsr=0x402, iova=0xffa00000, cbfrsynra=0x0, cb=1
To fix this, walk the map with a stride of 3 + '#iommu-cells' of the
referenced IOMMU and take the SID from the first specifier cell, which is
all the BDF to SID table needs. Validate the layout instead of trusting
the array size. Also, preserve the legacy behavior of the old DTs by
detecting the same pattern that of_check_bad_map() recognizes and
falling back to a stride of four.
Fixes: 4c9398822106 ("PCI: qcom: Add support for configuring BDF to SID mapping for SM8250")
Reported-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Tested-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Link: https://patch.msgid.link/20260907143349.317495-1-mani@kernel.org
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HDMA supports configurable DMA channel register space
separation which ranges from 256B to 32KB. Current implementation
supports 256B as default for DMA channel register space.
CPM6 supports the selection of channel register space via VSEC.
The default value for channel register space for CPM6 is 512B.
Updated the functions and methods to calculate the DMA channel
registers base address as per the selected channel separation
available as part of 'ch_space_sz'. Removed the unused function
__dw_regs() and structs, namely dw_hdma_v0_ch and dw_hdma_v0_regs.
Signed-off-by: Devendra K Verma <devverma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260907101213.1917064-3-devverma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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states
Per PCIe spec r6.0, sec 5.5.4:
If setting either or both of the enable bits for PCI-PM L1 PM Substates,
both ports must be configured as described in this section while in D0.
Currently, the callers of pci_enable_link_state_locked() (vmd, pcie-qcom)
transition the device to D0 themselves before enabling the link state. But
this is easy to get wrong and has to be duplicated by every caller.
Move the D0 transition into the shared __pci_enable_link_state() helper so
that all three APIs pci_enable_link_state(), pci_enable_link_state_locked()
and pci_force_enable_link_state() perform it, and only when the PCI-PM L1
PM Substates are getting enabled.
Now that the helper handles the transition, drop the redundant D0
transition from the vmd and pcie-qcom callers.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260708-pci-aspm-fix-v3-3-6bd72451746e@kernel.org
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Add SoC-specific data for the RZ/G3L (R9A08G046) PCIe controller and
register its "renesas,r9a08g046-pcie" compatible string. RZ/G3L reuses
the RZ/G3E config init/deinit callbacks and power resets, with its own
L1-allow syscon offset and mask.
Also increase the timeout in rzg3s_pcie_set_max_link_speed() to fix
the "Failed to set max link speed" message seen on RZ/G3L.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260903133320.144245-3-biju.das.jz@bp.renesas.com
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rzg3s_pcie_init_irqdomain() installs chained handlers for the INTx
parent interrupts before creating the INTx irqdomain and initializing
MSI support.
If any subsequent step fails, such as obtaining an INTx IRQ,
creating the irqdomain, or initializing MSI, the error path returns
without removing any chained handlers that were already installed.
This leaves stale handler and data pointers attached to the parent
interrupts.
Add a helper to tear down the INTx IRQ setup, including removing the IRQ
domain and clearing the chained handlers. Use it to unwind partially
completed initialization and from the normal IRQ domain teardown path.
Fixes: 7ef502fb35b28 ("PCI: Add Renesas RZ/G3S host controller driver")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260811200013.185956-4-prabhakar.mahadev-lad.rj@bp.renesas.com
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platform_get_irq_byname() may return specific error codes such as
-EPROBE_DEFER, but rzg3s_pcie_init_irqdomain() replaces all failures
with -EINVAL.
This breaks probe deferral by preventing the driver core from retrying
probe once the interrupt provider becomes available.
Propagate the original error code instead.
Fixes: 7ef502fb35b28 ("PCI: Add Renesas RZ/G3S host controller driver")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260811200013.185956-3-prabhakar.mahadev-lad.rj@bp.renesas.com
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rzg3s_pcie_host_init_port() enables the PCIe reference clock using
clk_prepare_enable(), but if rzg3s_pcie_probe() subsequently fails, for
example because pci_host_probe() returns an error, the probe error path
only releases the clock handle with clk_put().
Balance clk_prepare_enable() by calling clk_disable_unprepare() in the
probe cleanup path before releasing the clock, ensuring the reference
clock is properly disabled on probe failure.
Fixes: 7ef502fb35b28 ("PCI: Add Renesas RZ/G3S host controller driver")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260811200013.185956-2-prabhakar.mahadev-lad.rj@bp.renesas.com
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All existing DTS users already name the INTx child node
"interrupt-controller". Use of_get_child_by_name() to find it instead
of assuming it is the first child node.
Signed-off-by: Zhengping Zhang <aquapinn@qq.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/tencent_5E7D6E7FB25B4CD732F08547C11F5DA24808@qq.com
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xgene_pcie_init_port() obtains and enables the controller clock manually.
When xgene_pcie_setup() or pci_host_probe() fails, probe returns without
disabling, unpreparing, or releasing the clock. A failed enable also leaves
the clk_get() reference unreleased.
Use devm_clk_get_enabled() so the clock is unwound automatically on probe
failure and device removal.
Fixes: 5f6b6ccdbe1c ("PCI: xgene: Add APM X-Gene PCIe driver")
Signed-off-by: Yuho Choi <dbgh9129@gmail.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260802221146.573233-1-dbgh9129@gmail.com
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