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path: root/drivers/gpu
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2026-10-01drm/amd/display: Remove unused copyright noticeJackson He
[Why & How] The copyright notice was carried over from code related to kernel floating-point support. The associated DC_FP_START() and DC_FP_END() macros are not present in SPL, so the notice is no longer applicable. Remove the unused copyright notice from spl_os_types.h. Signed-off-by: Jackson He <Jackson.He@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Samson Tam <samson.tam@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Program OPP formatter for plane-less ODM segmentsAshwin Santhosh
why: When a display is disabled the surviving DSC stream is committed with no planes but the dynamic ODM policy still expands it to a four to one combine. The added plane-less segments skip program_pipe so their OPP formatter is never configured. The DPG blank then feeds an unprogrammed formatter and the OPTC input underflows which flashes grey on screen. how: Program the OPP formatter for each plane-less OPP head in update_odm and update_odm_sequence the same way program_pipe does for planed pipes. Both function pointers are checked for null before calling. Every ODM segment now feeds valid data to the OPTC so the four to one combine no longer underflows. Signed-off-by: Ashwin Santhosh <Ashwin.Santhosh@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm: renesas: shmobile: stop using deprecated devm_drm_of_get_bridge()Luca Ceresoli
devm_drm_of_get_bridge() is deprecated, switch to of_drm_get_bridge_by_endpoint(). As of_drm_get_bridge_by_endpoint() returns a refcounted bridge, ensure it is put. drm_panel.h becomes unused, drop the include. Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Paul Cercueil <paul.cercueil@bootlin.com> Link: https://patch.msgid.link/20260929-drm-fix-of_get_bridge-build-regression-v2-7-6da431d8f180@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-10-01drm/bridge: dw-mipi-dsi2: stop using deprecated devm_drm_of_get_bridge()Luca Ceresoli
devm_drm_of_get_bridge() is deprecated, switch to of_drm_get_bridge_by_endpoint(). As of_drm_get_bridge_by_endpoint() returns a refcounted bridge, ensure it is put by using bridge.next_bridge. Reviewed-by: Paul Cercueil <paul.cercueil@bootlin.com> Link: https://patch.msgid.link/20260929-drm-fix-of_get_bridge-build-regression-v2-4-6da431d8f180@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-10-01drm/bridge: dw-mipi-dsi: stop using deprecated devm_drm_of_get_bridge()Luca Ceresoli
devm_drm_of_get_bridge() is deprecated, switch to of_drm_get_bridge_by_endpoint(). As of_drm_get_bridge_by_endpoint() returns a refcounted bridge, ensure it is put by using bridge.next_bridge. Fixes build failure when CONFIG_OF is disabled. Fixes: aa8a8c7e4641 ("drm/bridge: panel: move all code to drm_panel.c") Reported-by: Arnd Bergmann <arnd@kernel.org> Closes: https://lore.kernel.org/r/20260928161605.2271412-1-arnd@kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202609291109.9RGna4XZ-lkp@intel.com/ Link: https://lore.kernel.org/r/20260928161605.2271412-1-arnd@kernel.org Link: https://lore.kernel.org/oe-kbuild-all/202609291109.9RGna4XZ-lkp@intel.com/ Reviewed-by: Paul Cercueil <paul.cercueil@bootlin.com> Link: https://patch.msgid.link/20260929-drm-fix-of_get_bridge-build-regression-v2-3-6da431d8f180@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-10-01drm: verisilicon: stop using deprecated devm_drm_of_get_bridge()Luca Ceresoli
devm_drm_of_get_bridge() is deprecated, switch to of_drm_get_bridge_by_endpoint(). As of_drm_get_bridge_by_endpoint() returns a refcounted bridge, ensure it is put by using bridge.next_bridge. Fixes build failure when CONFIG_OF is disabled. Fixes: aa8a8c7e4641 ("drm/bridge: panel: move all code to drm_panel.c") Reported-by: Arnd Bergmann <arnd@kernel.org> Closes: https://lore.kernel.org/r/20260928161605.2271412-1-arnd@kernel.org Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202609291109.OIsGTysr-lkp@intel.com/ Closes: https://lore.kernel.org/oe-kbuild-all/202609290408.BOs7sk55-lkp@intel.com/ Reviewed-by: Icenowy Zheng <zhengxingda@iscas.ac.cn> Reviewed-by: Paul Cercueil <paul.cercueil@bootlin.com> Link: https://patch.msgid.link/20260929-drm-fix-of_get_bridge-build-regression-v2-2-6da431d8f180@bootlin.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-10-01drm/imx/lcdc: stop using deprecated devm_drm_of_get_bridge()Luca Ceresoli
devm_drm_of_get_bridge() is deprecated, switch to of_drm_get_bridge_by_endpoint(). As of_drm_get_bridge_by_endpoint() returns a refcounted bridge, ensure it is put. Fixes build failure when CONFIG_OF is disabled. Fixes: aa8a8c7e4641 ("drm/bridge: panel: move all code to drm_panel.c") Reported-by: Arnd Bergmann <arnd@kernel.org> Link: https://lore.kernel.org/r/20260928161605.2271412-1-arnd@kernel.org Acked-by: Maxime Ripard <mripard@kernel.org> Reviewed-by: Paul Cercueil <paul.cercueil@bootlin.com> Link: https://patch.msgid.link/20260929-drm-fix-of_get_bridge-build-regression-v2-1-6da431d8f180@bootlin.com [Luca: fixed conflict in imx_lcdc_probe] Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
2026-10-01drm/amdgpu: Reject UALink handle ioctl on devices without UALinkMukul Joshi
amdgpu_gem_ualink_handle_ioctl() dereferences adev->ualink.info before validating it, but that structure is only allocated when the UALink IP block is present, which is currently added only for GFX 12.1 only. The ioctl is registered for every amdgpu device with DRM_RENDER_ALLOW, so on any other ASIC a render node user can oops the kernel with a single call. Return -EOPNOTSUPP when the UALink software state is absent. Fixes: 15d1c306d829 ("drm/amdgpu: Add ioctl infra for exporting/importing UALink handles") Reported-by: Sashiko-bot <sashiko-bot@kernel.org> Closes: https://sashiko.dev/#/patchset/20260914054604.12850-1-kmehltretter@gmail.com?part=1 Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Skip HDMI FRL status polling while link is downFangzhi Zuo
[WHY] Hotplugging an HDMI FRL sink can wedge DMCUB when a poll-driven retrain lands on a link whose PHY has just been torn down. The status polling path can program PHY EQ on the disabled PHY, after which the sink SCDC reads back version 0 and the display fails to light up. [HOW] Skip FRL status polling unless the link is actively driving a stream. The check runs under dc_lock, so it is serialized with link detection and modesets while the PHY is being torn down. Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Disable gamcor light sleep before gamcor programAlvin Lee
[Description] - Gamcor light sleep must be disabled before gamcor programming - Mirror the programming sequence for DSCL light sleep - Create a dcn60 version for gamcor programming - Make dcn30 helper functions public so they can be called from the new dcn60 function Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: implement workaround for sdma dcc corruptionPierre-Eric Pelloux-Prayer
For unknown reasons, on gfx12 using multiple entities can causes random corruption of BOs with DCC. This workaround seems to prevent the issue until the root cause is understood and fixed. Link: https://gitlab.freedesktop.org/drm/amd/-/work_items/5663 Fixes: 3a6f6eeb3db5 ("drm/amdgpu: give ttm entities access to all the sdma scheds") Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Delete unimplemented GMC v9 soft_reset() codeTimur Kristóf
The soft_reset() function for GMC (memory controller) block of Vega has never been implemented, and there are no plans to implement it. Let's delete this function, it doesn't do anything and also isn't called from anywhere. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Delete GMC v6-v7 soft_reset() codeTimur Kristóf
Note that the soft reset code for GMC v6-v7 was never called from anywhere, so there is no loss of functionality from this commit. The implementation looks plausible but it was never enabled or tested, and unlikely to be useful. We should only reset the memory controller during ASIC reset and otherwise leave it alone. Resetting the memory controller can break everything and risks losing the contents of VRAM (it's unclear if VRAM is lost or not, but it's likely). Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/gfx: add a gfx ME pipe reset capability helperJesse Zhang
Use gfx_supported_reset's PER_PIPE bit to report GFX pipe reset support through a shared helper. Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Keep public DC lifecycle APIs stable beside Core 2Cheng, Tony
DMs still call dc_hardware_init and dc_hardware_release while Core 2 lands next to legacy. Those entry points live in dc/dc_api_dispatch: LEGACY calls the old bodies directly, CORE2 uses core2_funcs. dc_create allocates struct dc2 and returns the inner dc (TO_DC2). The shim only records selection; dc_construct still constructs Core2. No dispatch fields on public struct dc, and no architect spec edits. TO_DC2 is a typed upcast (struct dc is the first member of struct dc2). Shim headers are included for UNIT_TEST as well as production so TO_DC2 is defined when core_gtest compiles dc.c. Assisted-by: Cursor:cursor Signed-off-by: Cheng, Tony <Tony.Cheng@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Change default SR z8 exit/enter valueFudongwang
[WHY+HOW] According to HW, change default z8 enter/exist for dcn314. SR Z8 exit = 268, change to 390. SR Z8 enter = 393, change to 601. Signed-off-by: Fudongwang <Fudong.Wang@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add dcn60 revision specific clock overridesDillon Varone
[WHY&HOW] Not all revisions require the same clock overrides. Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Add missing message to static_assertDominik Kaszewski
[Why & How] static_assert requires a message in older standards. Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Dillon Varone <dillon.varone@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Serialize HDMI FRL status polling against link detectFangzhi Zuo
[WHY] The HDMI FRL status polling work can run concurrently with link detect after an unplug/replug. Both paths access the same link through DDC and may perform FRL link training, while the polling path also reads link state without holding dc_lock. [HOW] Use mutex_trylock() to serialize the complete link walk, FRL status polling, and retraining sequence with dc_lock. If the lock is busy, defer the background poll to the next 200ms cycle instead of blocking an active detect, modeset, or flip. Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Fix DCN60 UTM QoS override for invalid PMFW tableWenjing Liu
[Why] The QoS model override for a display IP block was silently skipped whenever the firmware-populated table was invalid. [How] Always re-point the bandwidth params at the driver's own persistent QoS model storage before applying the override, instead of returning early when the firmware-populated model is NULL. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Consolidate bandwidth overridesWenjing Liu
[Why] Bandwidth overrides must be applied in a defined order so debug settings are reflected in the final parameters. [How] Group clock adjustments with the clock table override and derive the final mode limits after all clock table changes. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Synchronize UTM overrides with SMUWenjing Liu
[Why] Keep the display QoS model and firmware table consistent when test overrides are enabled. [How] Serialize the overridden QoS values into a dedicated transfer buffer and send the table after clock initialization. Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/display: Move struct dtbclk_dto_params to dc_hw_types.hTony Cheng
This can simplify includes Assisted-by: Cursor:composer-2.5 Signed-off-by: Tony Cheng <tony.cheng@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Reviewed-by: Jun Lei <jun.lei@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: specify cwsr_enable usage docEric Huang
to prevent misunderstanding in cwsr off case. Signed-off-by: Eric Huang <jinhuieric.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdkfd: Fix always mapped range mapping to all ACCESS GPUsAndrew Martin
CWSR ranges use the always mapped flag and only need a mapping on the GPU running the queue. However, svm_range_validate_and_map now updates the mapping on every GPU with the ACCESS attribute, which is all supported GPUs when XNACK is on. After the range is prefetched to VRAM, those GPUs may span different XGMI hives, so the page owner mismatches and is set to NULL. hmm_range_fault then tries to migrate the VRAM pages back to system memory, but svm_migrate_to_ram skips it because migrating pages back to system memory is not allowed while the GPU mapping is being updated, so the CPU page fault is never resolved. Only map to the ACCESS GPUs if the range is not mapped to any GPU and is not in VRAM. Fixes: b96f26104946 ("drm/amdkfd: Unmap svm range from GPU set to no-access") Signed-off-by: Andrew Martin <andrew.martin@amd.com> Assisted-by: Claude:claude-opus-5 Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0 supportHawking Zhang
Add initial implemenation for the new generation of mmhub Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mmhub v5_0_1 ip headers v3Alex Deucher
Add header files for mmhub v5_0_1 register offsets and shift masks v2: Update mmhub ip headers to BTO version v3: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: use PCRU0 C2PMSG for Uniras on psp v15_0_3Candice Li
Add a dedicated ras_psp_v15_0_3 ip_func using PCRU0 C2PMSG_67/127 for psp ring wptr and RAS capability query. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for psp v15_0_3Gangliang Xie
add uniras support for psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for nbio v7_10_0Gangliang Xie
add uniras support for nbio v7_10_0 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for smu v15_0_3Gangliang Xie
add uniras support for smu_v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for GC 13Gangliang Xie
add uniras support for GC 13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/ras: add support for umc v13Gangliang Xie
add uniras support for umc v13 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: skip vpe dpm enable if dpm_enabled flag is falseLin Cao
amdgpu_dpm_enable_vpe() should be skipped if dpm_enabled is false Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Allocate VPE cmdbuf from VRAMLin Cao
PSP should not accept a GART VA directly from VF Add logical to allocate VPE cmdbuf from VRAM Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.1 supportCaden Chien
This initializes VPE IP version 3.0.1 Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/vpe: add vpe v3.0.0 supportCaden Chien
This patch adds support for vpe v3.0.0 with new structs and ip functions Signed-off-by: Caden Chien <chih-wei.chien@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add vpe v3_0_0 ip headers v4Hawking Zhang
Add header files for vpe v3_0_0 register offsets and shift masks v2: Update vpe ip headers to LSC version v3: Update vpe ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu/psp: wait for TOS ready on all AIDs in v15_0_3 ring createEmily Deng
When aid_mask is set, poll MP0 C2PMSG_64 on each AID instance before creating the PSP GFX command ring. Single-die paths are unchanged. Signed-off-by: Emily Deng <Emily.Deng@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add VPE FW list to PSP_15_0_3 under SRIOVLin Cao
Add VPE FW list including VPE_CTX and VPE_CTL Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add GFX FW list to PSP_15_0_3 under SRIOVLin Cao
[Why] Under SRIOV VF, GFX firmware are required to loaded. [How] Add GFX FW list. FW contains: PFP ucode, PFP data P0-P1 ME ucode, ME data P0-P1 MEC ucode, MEC data P0-P7 MES SCH ucode and data MES KIQ ucode and data Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add new MEC2 firmware loading frameworkLin Cao
Add ucode loading support for MEC pipe stacks P4-P7: - add GFX_FW_TYPE_RS64_MEC_P4..P7 firmware types - add AMDGPU_UCODE_ID_CP_RS64_MEC_P4..P7 ucode ids - handle P4-P7 in ucode name/init, psp fw type Signed-off-by: Yifan Zha <Yifan.Zha@amd.com> Signed-off-by: Yiqing Yao <yiqing.yao@amd.com> Signed-off-by: Lin Cao <lincao12@amd.com> Reviewed-by: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: support MP5 in firmware info queriesYang Wang
Handle AMDGPU_INFO_FW_MP5 in the firmware query path and report the MP5 firmware version in the debugfs firmware_info output. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: expose MP5 firmware version in sysfsYang Wang
Add an mp5_fw_version attribute to the fw_version sysfs group, so userspace can read the MP5 firmware version. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min<Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add infrastructrure for handling mp5 firmwareFrank Min
Add framework for MP5 firmware. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add ta loading in psp v15_0_3Gangliang Xie
add ta loading in psp v15_0_3 Signed-off-by: Gangliang Xie <ganglxie@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: fix ASP 15.0.3 runtime DB offsetYang Wang
ASP 15.0.3 stores the PSP runtime database at a fixed 64KB offset from the IP discovery table, not at the legacy offset from the end of VRAM. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-By: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add firmware type retrieval in PSP v15.0.3Frank Min
Add firmware type retrieval in PSP v15.0.3 to adapt psp fw updates Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add support for PSP version 15.0.3Frank Min
Add support for PSP version 15.0.3 v2: fix psp 15.0.3 C2P message reg access issue Signed-off-by: Frank Min <Frank.Min@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: Add mp v15_0_3 ip headers v4Hawking Zhang
Add header files for mp v15_0_3 register offsets and shift masks v2: Update mp ip headers to LSC version v3: Update mp ip headers to BTO version v4: Update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>