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path: root/drivers/gpu/drm/i915/display/intel_cx0_phy.c
AgeCommit message (Expand)Author
12 hoursMerge branch 'drm-next' of https://gitlab.freedesktop.org/drm/kernel.gitMark Brown
34 hoursdrm/i915/cx0_phy: Fix ARL-S host bridge detectionDnyaneshwar Bhadane
2026-09-21drm/i915: use string choice helpersLalit Shankar Chowdhury
2026-08-31drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequencySuraj Kandpal
2026-08-12drm/i915/cx0: program DDI_CLK_VALFREQ with DDI clock frequencySuraj Kandpal
2026-06-16drm/i915/cmtg: Set CMTG clock selectAnimesh Manna
2026-05-13drm/i915/display: add typedef for intel_reg_t and use itJani Nikula
2026-04-24drm/i915/ddi: add wrapper for calling ->get_buf_trans() hookJani Nikula
2026-03-24drm/i915/lt_phy: Readout lane countMika Kahola
2026-01-27drm/i915/cx0: Rename intel_clear_response_ready flagSuraj Kandpal
2026-01-27drm/i915/cx0: Clear response ready & error bitSuraj Kandpal
2026-01-20drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tablesMika Kahola
2026-01-20drm/i915/cx0: Drop C20 25.175 MHz rateMika Kahola
2026-01-20drm/i915/cx0: Verify C10/C20 pll dividersMika Kahola
2026-01-20drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programmingMika Kahola
2026-01-20drm/i915/cx0: Fix HDMI FRL clock ratesMika Kahola
2026-01-20drm/i915/display: Add helper function for fuzzy clock checkMika Kahola
2026-01-20drm/i915/cx0: Create macro around PLL tablesMika Kahola
2026-01-20drm/i915/cx0: Drop encoder from port clock calculationMika Kahola
2026-01-20drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculationMika Kahola
2026-01-20drm/i915/cx0: Move C20 port clock calculationMika Kahola
2026-01-20drm/i915/cx0: Move C10 port clock calculationMika Kahola
2025-12-24drm/i915/cx0: Use the consolidated HDMI tablesSuraj Kandpal
2025-12-19drm/i915/cx0: Toggle powerdown states for C10 on HDMIGustavo Sousa
2025-12-19drm/i915/cx0: Use a more accurate message for powerdown change failureGustavo Sousa
2025-12-10drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug messageImre Deak
2025-12-01drm/i915/power: convert intel_wakeref_t to struct ref_tracker *Jani Nikula
2025-11-21drm/i915/cx0: Read out power-down state of both PHY lanes for reversed lanesImre Deak
2025-11-21drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0Imre Deak
2025-11-19drm/i915/cx0: Enable dpll framework for MTL+Mika Kahola
2025-11-19drm/i915/cx0: Add MTL+ Thunderbolt PLL hooksImre Deak
2025-11-19drm/i915/cx0: Add MTL+ .enable_clock/.disable clock hooks on DDIMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .get_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Add MTL+ .dump_hw_state hookMika Kahola
2025-11-19drm/i915/cx0: Update C10/C20 state calculationMika Kahola
2025-11-19drm/i915/cx0: Remove state verificationMika Kahola
2025-11-19drm/i915/cx0: Print additional Cx0 PLL HW stateImre Deak
2025-11-19drm/i915/cx0: Zero Cx0 PLL state before compute and HW readoutImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL port clock from PLL stateImre Deak
2025-11-19drm/i915/cx0: Determine Cx0 PLL DP mode from PLL stateImre Deak
2025-11-19drm/i915/cx0: Read out the Cx0 PHY SSC enabled stateImre Deak
2025-11-19drm/i915/cx0: Sanitize C10 PHY PLL SSC register setupImre Deak
2025-11-19drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Move definition of Cx0 PHY functions earlierImre Deak
2025-11-19drm/i915/cx0: Track the C20 PHY VDR state in the PLL stateImre Deak
2025-11-19drm/i915/cx0: Sanitize calculating C20 PLL state from tablesImre Deak
2025-11-19drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flagImre Deak
2025-11-19drm/i915/cx0: Factor out C10 msgbus access start/end helpersImre Deak
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_ms()Ville Syrjälä
2025-11-11drm/i915/de: Use intel_de_wait_for_{set,clear}_us()Ville Syrjälä