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path: root/drivers/gpu/drm/amd/pm
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24 hoursdrm/amd/pm: mark the current DPM clock level activeKevin Wang
PMFW can report clocks outside or between advertised DPM levels. Report a clock below DPM0 as a special active S level. Mark the nearest level active for a discrete DPM table. Clamp a clock above the table range to the maximum DPM level. Keep reporting the actual clock for a fine-grained DPM table. Signed-off-by: Kevin Wang <kevin.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: propagate errors when forcing SMU11 clock levelsAvi Weiss
navi10_force_clk_levels() and sienna_cichlid_force_clk_levels() return success when a DPM frequency lookup or soft frequency range update fails. smu_force_smuclk_levels() then records the requested clock mask even though the operation failed. Return the helper error from both callbacks instead to improve observability. No obvious reason to clobber the return values here. Fixes: db439ca21b81f ("drm/amd/powerplay: add function force_clk_levels for navi10") Fixes: b455159c05313 ("drm/amdgpu/powerplay: add initial swSMU support for sienna_cichlid (v2)") Signed-off-by: Avi Weiss <thnkslprpt@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amdgpu/pm: move smu_feature_init to smu_early_initCe Sun
RAS early init executes prior to smu_sw_init, leaving feature_num as 0 and triggering invalid bitmap operations. Signed-off-by: Ce Sun <cesun102@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: add zero fan stop temperature support on smu 14.0.2Kenneth Feng
add zero fan stop temperature support on smu 14.0.2 Closes: https://gitlab.freedesktop.org/drm/amd/-/work_items/5905 Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: Notify node unload during driver unloadAsad Kamal
Notify node unload on smu_v15_0_8 during driver unload Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: Add store npm limit functionAsad Kamal
Add npm store limit function and use it to update current power limit Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: Add NPM metrics reads and SetNpmLimitAsad Kamal
Add NPM metrics reads, SetNpmLimit for smu_v15_0_8 and enable NPM feature based on system metrics version v2: Move init caps during pptable init Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: Add set_npm_limit functionAsad Kamal
Wire up the set_npm_limit callback from pp_funcs through smu/dpm to the PPT layer. Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
24 hoursdrm/amd/pm: Update smu_v15_0_8 PMFW headersAsad Kamal
Update smu_v15_0_8 PMFW headers to include NPM metrics Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/pm/si: Fix updating clock limits on AC/DCTimur Kristóf
Assume that the AC limits are the maximum of all power states, and the DC limits are the maximum of battery power states. This shouldn't make any difference in practice, but is cleaner and more robust against bogus information in the VBIOS. Fixes: e6c5d36756e7 ("drm/amd/pm/si: Fix updating clock limits from power states") Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923120354.1027996-2-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/pm: Fix metrics formatting in SMUv15.0.8Lijo Lazar
Use the right formatting for some fields which are encoded in Q10 format. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amdgpu: add infrastructrure for handling mp5 firmwareFrank Min
Add framework for MP5 firmware. Signed-off-by: Frank Min <Frank.Min@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-10-01drm/amd/pm/si: Check AMD_IS_MOBILITY flag for PPSMC_SYSTEMFLAG_GPIO_DCTimur Kristóf
Unfortunately, some desktop boards eg. the FirePro D500 have the HARDWAREDC platform flag set and also have a battery power state configured in their VBIOS. This makes no sense for a desktop GPU and results in incorrect behaviour: the clocks are stuck at lowest. We observed that the kernel driver can work around the issue in two possible ways: 1. Set PPSMC_SWSTATE_FLAG_DC on all power states 2. Clear PPSMC_SYSTEMFLAG_GPIO_DC We think that the PPSMC_SYSTEMFLAG_GPIO_DC flag makes the SMC assume it's running on battery even though this is a desktop machine with no battery, and that's why it doesn't do DPM on power states without PPSMC_SYSTEMFLAG_GPIO_DC. Issue was uncovered by "Fix updating clock limits from power states" because previously the limits for the battery state were not tracked separately. However, battery power state has lower frequencies and voltages, so the kernel doesn't set the DC flag on the current power state anymore. That causes the SMC to be stuck on the lowest clocks. Let's clear PPSMC_SYSTEMFLAG_GPIO_DC on desktop GPUs. We can use the AMD_IS_MOBILITY flag to determine that. Fixes: e6c5d36756e7 ("drm/amd/pm/si: Fix updating clock limits from power states") Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/16352 Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/20260923120354.1027996-1-timur.kristof@gmail.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Add NPM status sensorLijo Lazar
The logic for checking whether NPM is enabled/disabled stays within the particular IP version. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Create NPM sysfs files from capabilityLijo Lazar
Advertise each NPM board attribute from a per-field R/W bitmap instead of probing a single sensor. SMU 13.0.6/13.0.12 reports the cap only when NPM metrics and MaxNodePowerLimit are present. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Assisted-by: Cursor Grok 4.6 Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Drop redundant power_context_sizeLijo Lazar
The size is stored and cleared in init/fini but never used to for anything else like copy. Drop the size and use pointer for init/fini checks. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Fix SMUv14/15 power context allocationLijo Lazar
Allocate the right power context objects in smu v14 and smu v15 Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-23drm/amd/pm: Add GetRmaStatus messageYiPeng Chai
Add GetRmaStatus message for smu_v13_0_12 and smu_v15_0_8. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Kevin Wang <kevin.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amdgpu: Extend logical to device instance lookup to all devicesTvrtko Ursulin
A subset of supported devices can have a mismatch between the logical and device engine instance numbers which the driver currently solves by a combination of lookup table generated at driver init time, and a conditionally set vfunc checked and used at runtime to do the lookup. As the requirement to do these lookups is relatively widespread in the code base, plus the fact the mapping table is already allocated for all possible hw ips and instances, we can significantly streamline them by initializing the said lookup table unconditionally to the predominant "identity map" (logical instance numbers equal to device instances), and allow affected parts to re-configure the table based on their configuration. The effect is that for each lookup site we replace the conditional followed by a indirect function call with a simple two-dimensional table lookup. Bloat-o-meter agrees the savings are significant: add/remove: 13/12 grow/shrink: 23/279 up/down: 51626/-198973 (-147347) ... Total: Before=10139692, After=9992345, chg -1.45% Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/pm: delete a stray tabDan Carpenter
This tab was accidentally added in commit 6c9e0328d1de ("drm/amd/pm: refactor PPT limits by controller and power source"). Delete it. Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/pm: bound SCLK FCW range entries to the table sizeHari Mishal
atomctrl_get_smc_sclk_range_table() copies ucSclkEntryNum entries from the VBIOS SMU_Info table into pp_atom_ctrl_sclk_range_table. Both the source (asSclkFcwRangeEntry[]) and destination (table->entry[]) arrays are fixed at MAX_SCLK_RANGE (8) entries, but ucSclkEntryNum is an unchecked u8 read straight from the VBIOS, so it can be up to 255. The destination is stack-allocated in both callers (polaris10_get_sclk_range_table(), vegam_get_sclk_range_table()), so a count above 8 overflows a stack buffer, not just a heap read. Reject counts above MAX_SCLK_RANGE rather than clamping to it. Only one version of this VBIOS struct (ATOM_SMU_INFO_V2_1) has ever existed, so a count above 8 corresponds to no legitimate table format and means either a corrupted or a tampered VBIOS. Fixes: a23eefa2f461 ("drm/amd/powerplay: enable dpm for baffin.") Assisted-by: gkh_clanker_t1000 Signed-off-by: Hari Mishal <harimishal1@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17drm/amd/pm: report energy accumulator for smu 14.0.3Kevin Wang
add energy accumulator on pmfw 0x00685000 and above version. Signed-off-by: Kevin Wang <kevin.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-17Merge tag 'amd-drm-next-7.4-2026-09-10' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/amdgpu/kernel into drm-next amd-drm-next-7.4-2026-09-10: amdgpu: - Freesync fixes - GPUVM fix - Debugfs fixes - HDMI updates - IPS fix - GPU reset fix - RGB quantization fixes - SMU 13.0.x fixes - MES updates - UserQ updates - UVD fix - Various bounds checks - DML fixes - DCN 6 updates - NBIO 7.11.5 support - Audio fixes - More display KUnit tests - SMU 15 updates - RAS updates - VCN 5.0.2 updates - JPEG 5.0.2 updates - DCN 4.2 updates - PSR fixes - Misc cleanups - PSP 15.0.8 updates - RAS BERT support - RAS CPER updates - vblank fixes - LSDMA updates - GC 12.1 updates - MMHUB 4.2 updates - NBIO 6.3.2 updates - SMU 15.0.8 updates - IP discovery updates - GPU spatial partitioning updates - HDMI 2.1 freesync support - HDMI 2.1 ALLM support - HDMI 2.1 VRR support - Require jobs for IBs - Enable FRL for HDMI - MES oversubscription fixes - IH 6-7 updates - GMC 11-12 fault handling updates - Fixed point cleanup - Backlight fixes - GPUVM cleanup - Devcoredump fixes - UALoE (UALink over Ethernet) Support - SDMA userq fixes - GC 8 fix amdkfd: - Various bounds checks - SVM fixes - GC 12.1 updates - MES updates - Trap handler fixes - Debugfs fixes drm: - Add gem callback for when handle count goes to 0 - Rust fix UAPI: - INFO IOCTL fix for 32 bit userspace on 64 bit kernel - Add syncobj_points to USERQ signal ioctl Proposed userspace: * radeonsi NV_timeline_semaphore https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37335 * RADV user queues https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40808 - Add UALink support IOCTLs Proposed userspace: https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L971 https://github.com/ROCm/rocm-systems/blob/35959f8e1260c7cee3e51a740e320be3856ee4ff/projects/rocr-runtime/libhsakmt/src/memory.c#L1036 Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://patch.msgid.link/20260910213040.826425-1-alexander.deucher@amd.com
2026-09-10drm/amd/pm: report energy accumulator for smu 13.0.0Kevin Wang
add energy accumulator on pmfw 0x004e8600 and above version. Signed-off-by: Kevin Wang <kevin.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-10drm/amd/pm: fix gpu metrics energy accumulator for smu 13.0.0/13.0.7Kevin Wang
GPU metrics v1.3 defines energy_accumulator as a 64‑bit field. The unsupported‑firmware code path assigns UINT_MAX, which is neither the full‑width invalid value for this field nor its default value. Fixes: 8de9edb35976 ("drm/amd/pm: remove invalid gpu_metrics.energy_accumulator on smu v13.0.x") Signed-off-by: Kevin Wang <kevin.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-10drm/amdgpu: skip gfx switch_power_profile during GPU resetPrike Liang
During resume from GPU reset, the gfx idle work may invoke switch_power_profile before the reset completes. This causes the following assert error because the register access occurs without first releasing the GPU reset semaphore: [ 1576.768935] CR2: 0000559ea133ead0 CR3: 00000002e6c42000 CR4: 0000000000350ef0 [ 1576.768940] Call Trace: [ 1576.768944] <TASK> [ 1576.768953] amdgpu_device_rreg+0x21/0x50 [amdgpu] [ 1576.769158] smu_msg_v1_send_msg+0x1a4/0x6e0 [amdgpu] [ 1576.769437] smu_cmn_send_smc_msg_with_params_ext+0xba/0x120 [amdgpu] [ 1576.769721] smu_cmn_send_smc_msg_with_param+0x33/0x40 [amdgpu] [ 1576.769993] smu_v13_0_0_set_power_profile_mode+0x192/0x2b0 [amdgpu] [ 1576.770267] smu_bump_power_profile_mode+0x5d/0x80 [amdgpu] [ 1576.770538] smu_switch_power_profile+0xa4/0xf0 [amdgpu] [ 1576.770839] amdgpu_dpm_switch_power_profile+0x6f/0x90 [amdgpu] [ 1576.771210] amdgpu_gfx_profile_idle_work_handler+0xe9/0x130 [amdgpu] [ 1576.771460] process_one_work+0x23e/0x6f0 [ 1576.771491] worker_thread+0x1c4/0x380 [ 1576.771506] kthread+0x10c/0x150 [ 1576.771512] ? __pfx_worker_thread+0x10/0x10 [ 1576.771518] ? __pfx_kthread+0x10/0x10 [ 1576.771530] ret_from_fork+0x314/0x390 [ 1576.771537] ? __pfx_kthread+0x10/0x10 [ 1576.771546] ret_from_fork_asm+0x1a/0x30 Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-10drm/amd/pm: Separate PPT limit restore from smu_set_ac_dcLijo Lazar
Move the PPT limit restore out of smu_set_ac_dc. Keep smu_set_ac_dc only for switching the power source. Drop the restore ppt limit policy parameter and add the restore logic to ac/dc notification path. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-09-04treewide: refresh kmalloc_obj() conversionsKees Cook
This is another run of the Coccinelle script for converting kmalloc() family of allocations to kmalloc_obj() via the existing rules in scripts/coccinelle/api/kmalloc_objs.cocci This catches both the set of kmalloc() uses added since the first kmalloc_obj() conversions in v7.0 and adds a large group missed in the first pass due to Coccinelle not interacting well with the cleanup.h scoped_...() family of macros[1]. I worked around this with spatch's "--macro-file" argument to a file with all the scoped_...() macros mapped to Coccinelle's YACFE_ITERATOR[2] as that was the closest viable control flow indicator I could find. Build tested allmodconfig on x86, arm64, arm, loongarch, mips, powerpc, riscv, and s390 with no new warnings. Link: https://lore.kernel.org/lkml/202609021314.8A9C0B8@keescook/ [1] Link: https://github.com/coccinelle/coccinelle/blob/master/standard.h [2] Signed-off-by: Kees Cook <kees+treewide@kernel.org>
2026-09-02drm/amd/pm: Implement notify_ac_dc callback for swsmuLijo Lazar
Wire up the notify_ac_dc pp_funcs callback for swsmu instead of special-casing is_support_sw_smu in the ACPI event handler. This keeps AC/DC transition notification through the same callback path as used by legacy powerplay and legacy-dpm backends. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: add 5s custom timeout for unload messagesAsad Kamal
The default SMU message timeout may be too short for the PrepareMp1ForUnload message on smu_v15_0_8, leading to spurious -ETIME errors under load or slow firmware response conditions. Introduce SMU_V15_0_8_MSG_TIMEOUT_US (5 seconds) and apply it to: - smu_v15_0_8_notify_unload(): switch from smu_cmn_send_smc_msg() to smu_cmn_send_smc_msg_with_params_ext() to pass the explicit timeout. v2: Use c2pmsgctl and args directly (Lijo) Signed-off-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/ras: support multi-parameter communication with mp1 in ras_mp1_v15_0YiPeng Chai
support multi-parameter communication with mp1 in ras_mp1_v15_0. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: update RAS-specific interface to support multi-parameterYiPeng Chai
Update the dedicated smu ras message interface to accept multiple parameters on each call. v2: Add input parameter validation. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Yang Wang <kevinyang.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amdgpu: Remove is_idle (trivial cases)Dr. David Alan Gilbert
The is_idle method on amd_ip_funcs is never called. Remove the trivial cases where either: a) It's just a return true function that can be deleted together with the .is_init = b) The function is called somewhere else, so we just remove the assignment. Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: Remove unused functions in smu_v15_0Srinivasan Shanmugam
smu_v15_0_load_microcode() and smu_v15_0_set_single_dpm_table() are not called anywhere; the latter is a carry-over from a previous version. The static helpers smu_v15_0_get_dpm_freq_by_index(), smu_v15_0_get_dpm_level_count() and smu_v15_0_get_fine_grained_status() were only called from smu_v15_0_set_single_dpm_table(), so remove those as well. Remove all functions along with their declarations from the header. Fixes: c7fc0f372374 ("drm/amd: Enable SMU 15_0_0 support") Fixes: f7bee962d92a ("drm/amd/pm: Update dpm table structs for smu_v15_0") Reported-by: Dan Carpenter <error27@gmail.com> Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-25drm/amd/pm: compute SMU v15.0.0 gpu_metrics from accumulator tableShubhankar Milind Sardeshpande
Rework smu_v15_0_0_get_gpu_metrics() to derive values from the raw accumulator double-buffer instead of the firmware-computed SmuMetrics_t snapshot: - Add SMU_V15_IOD_AVG()/SMU_V15_CORE_AVG() helpers: wrapping_sub() delta over the sampling window, scaled by the caller's unit factor, then descaled from Q10 fixed-point with >>10 (scale before shift to keep sub-unit precision); typeof() preserves each field's width. - Reuse the same macro in smu_v15_0_0_compute_all_metrics(), dropping the open-coded div_u64(..., 1024) boilerplate. - Drop the unused smu_v15_0_0_get_gpu_metrics_table() helper and the SMU_TABLE_SMU_METRICS allocation. Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Assisted-by: Claude:claude-opus-4.8 Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-20BackMerge tag 'v7.2' into drm-nextDave Airlie
Linux 7.2 There was a lot of conflicts this round between fixes and next, and I'd like to get the merge resolutions that we have in drm-tip. Signed-off-by: Dave Airlie <airlied@redhat.com>
2026-08-12drm/amd/pm: silence uninitialized variable warningsDan Carpenter
Smatch complains that: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu15/smu_v15_0_8_ppt.c:1964 smu_v15_0_8_set_performance_level() error: uninitialized symbol 'ret'. In this line there is an "if (ret)" condition where "ret" is either zero or uninitialized. Initialize "ret" at the start of the function to avoid a potential uninitialized variable bug. But also delete the condition since it is never true. Fixes: 422b399b09c7 ("drm/amd/pm: Add od_edit_dpm_table support") Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amdgpu: Enable GFXOFF functionality for SMU IP v15.0.5Shubhankar Milind Sardeshpande
Add clockgating and powergating flags for GC 11.5.6 and allow/disallow GFXOFF for SMU 15.0.5 Signed-off-by: Shubhankar Milind Sardeshpande <Shubhankar.MilindSardeshpande@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amd/pm: Keep sub-degree precision in Q10 temperaturesLijo Lazar
The Q10 temperatures were rounded to whole degrees before being scaled to millidegrees, losing sub-degree precision. Convert them while preserving the fractional part. Also, use the standard MILLIDEGREE_PER_DEGREE to represent SMU_TEMPERATURE_UNITS_PER_CENTIGRADES. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amd/pm: Keep sub-watt precision in Q10 socket powerLijo Lazar
The Q10 socket power was rounded to whole watts before scaling to milliwatts, so the reported value lost its sub-watt precision. Add SMUQ10_TO_MILLIWATT to convert while keeping the fractional bits. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-12drm/amd/pm: Simplify SoC power printing in debugfsLijo Lazar
Convert SoC power directly from milliwatts using MILLIWATT_PER_WATT and remove redundant variables. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: use find_clk_level() for DPM level markingPriya Hosur
Replace the simple exact-match loop in emit_clk_levels with a call to smu_v14_0_0_find_clk_level() introduced in patch 1. The helper already handles both exact and closest-match semantics. Build a stack-local frequency table from the DPM levels (using reverse index for SMU_MCLK since MemPstateTable stores levels high-to-low), then call the helper once to find the active level. The SMU reports time-filtered average frequencies that often do not match any DPM table entry exactly. Without closest-match fallback, MCLK, FCLK and other clocks show DPM levels but never display the * marker, breaking userspace tools that rely on it to identify the active frequency. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: add SMU_DCEFCLK support in DPM frequency queriesPriya Hosur
Add SMU_DCEFCLK case to smu_v14_0_1_get_dpm_freq_by_index and smu_v14_0_0_get_dpm_freq_by_index using DcfClocks[] with NumDcfClkLevelsEnabled bounds check. Add matching case in both get_dpm_level_count functions. Add SMU_DCEFCLK case in emit_clk_levels to list DCEF DPM levels. No * marker is emitted since SmuMetrics_t has no DcfclkFrequency field (same firmware limitation as Phoenix). Without this, pp_dpm_dcefclk reports N/A on Strix Halo. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: add IP_VERSION(11,5,1) to vclk/dclk DPM sysfs whitelistsPriya Hosur
Add IP_VERSION(11,5,1) to pp_dpm_vclk and pp_dpm_dclk visibility whitelists so these sysfs entries are exposed on Strix Halo (GC 11.5.1). Add IP_VERSION(11,5,1) to pp_dpm_vclk1 and pp_dpm_dclk1 whitelists with the existing num_vcn_inst >= 2 guard since Strix Halo has two VCN instances. Without this, amd-smi reports N/A for VCLK0, VCLK1, DCLK0 and DCLK1 clocks. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: smu_v14_0_0: fix DCLK metric reporting via VCLK level indexPriya Hosur
SmuMetrics_t has no DclkFrequency field but DCLK and VCLK have separate DPM clock tables with different frequencies at each level. Introduce smu_v14_0_0_find_clk_level(), a shared helper that finds the closest DPM level for a given target frequency in a frequency array. For METRICS_AVERAGE_DCLK, use the helper to find the DPM level whose VCLK frequency matches the reported VclkFrequency and return the DCLK frequency at that same level index, since both clocks share the same level count (VcnClkLevelsEnabled / Vcn0ClkLevelsEnabled). The original code returned 0 for METRICS_AVERAGE_DCLK, which broke the active-level marker in pp_dpm_dclk entirely. Signed-off-by: Priya Hosur <Priya.Hosur@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: restore user PPT limits after GPU resetYang Wang
GPU reset reinitializes PMFW and reloads the platform power table. The saved user policy remains valid, but suspend-only restore does not run because adev->in_suspend is clear. Restore the active PPT policy from SMU late initialization while the device is in reset recovery. Route each value through the common range validation and ASIC setter before updating PMFW. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: refactor user PPT policy save and restoreYang Wang
The existing user policy representation has three ambiguities: - A numeric value cannot distinguish explicit zero from an unset policy. - One value per controller cannot preserve independent AC and DC requests. - Suspend-only restore misses runtime resume, GPU reset, and table reload. Refactor policy storage and restore as follows: - Store values and validity masks by power source and PPT controller. - Save writes against the active source. - Restore the active source after default SMU setup. - Reapply the target policy after live AC/DC transitions. - Use the target source default when no explicit request exists. The late-init path now covers system resume, runtime resume, GPU reset, and custom PPTable reload. Common code owns persistent policy; PMFW continues to own effective current limits. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: account for OD percentage in effective PPT limitsYang Wang
SMU 13.0.0, SMU 13.0.7, and SMU 14.0.2 represent limits above the message limit as a base value plus an overdrive percentage. GetPptLimit returns only the base, which causes two incorrect results: - hwmon reports the message limit instead of the effective limit. - Lowering the cap can leave the previous OD percentage active. Export the active overdrive table from PMFW and combine its PPT percentage with the message result. Use the exported percentage to clear OD state before programming a limit within the message range. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: refactor PPT limits by controller and power sourceYang Wang
The scalar PPT model has several structural limitations: - Controller identity, power source, capability, and PMFW state share the same fields. - Combined callbacks cannot address PPT0 and PPT1 independently. - Cached current limits can become stale after PMFW reset. Refactor the model around these rules: - Index ranges by AC/DC source and PPT0/PPT1 controller. - Store normal and overdrive capabilities separately. - Pass the controller to get and set callbacks. - Keep slow and fast names as semantic aliases. Assign each value to a single owner: - PPTable or platform initialization supplies constant capabilities. - PMFW supplies runtime state. - Common code selects the active source and overdrive range. Van Gogh defaults are initialized once, while firmware without PPT query support remains usable. Capable SMU 13.0.6 and SMU 15.0.8 platforms expose PPT1 through the same interface. A writable controller must also provide a setter callback. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-08-06drm/amd/pm: derive stable PPT limits from PPTableYang Wang
GetPptLimit reports mutable PMFW runtime state. Using that value for static capabilities causes two externally visible problems: - A userspace override changes the default reported through hwmon. - A firmware reset changes the advertised minimum or maximum range. Derive platform defaults and supported ranges from the driver PPTable for Sienna Cichlid, Navi10, Arcturus, and Aldebaran. Reserve PMFW queries for the effective current limit. Runtime policy can no longer redefine immutable platform capabilities. Signed-off-by: Yang Wang <kevinyang.wang@amd.com> Reviewed-by: Kenneth Feng <kenneth.feng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>