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The Clock and Reset Unit (CRU) in the Anlogic DR1V90 SoC provides
management for the clock and reset.
The clock driver includes support for:
- Generic clocks: fixed-factor, divider, mux and gate.
- PLL: "nm" type (parent * n / m) and "c" type (parent / c). These PLLs
are set up by the FSBL and mared as "don't touch" in the datasheet, so
only the recal_rate() op is provided.
- Divider with gate: support both division and gating (by setting value
to 0); some of them require a minimum divider value to avoid timing
issues.
This also prepares the structure for the reset controller support,
registering an auxiliary device for resets.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Brian Masney <bmasney@redhat.com>
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